Patent
1995-02-10
1996-06-11
Ellis, Richard L.
G06F 932, G06F 9312
Patent
active
055265006
ABSTRACT:
Pipeline structure that is arranged to allow 1.5 cycle access time for both data and instruction cache without imposing additional instruction step delays than that imposed by data and instruction cache that have 1 cycle access time. Half cycle pulses are produced to allow execution of various instructions in 0.5 cycles. A bypass signal is generated to allow data from a current load instruction to be available for a second subsequent instruction even though the access time for data cache is 1.5 cycles. Additionally, a branch address is available for a third subsequent instruction even though instruction cache access time is 1.5 cycles. The present invention shows the initiation of an instruction step for each cycle and 1.5 cycle access time for cache memory. The present invention can also be implemented by implementing an instruction every 2 cycles and providing 3 cycle access time for cache memory.
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DeLano Eric R.
Hotchkiss Thomas R.
Knebel Patrick
Simpson R. Craig
Tanksalvala Darius F.
Ellis Richard L.
Hewlett--Packard Company
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