System for obtaining correct byte addresses by XOR-ING 2 LSB bit

Details System for obtaining correct byte addresses by XOR-ING 2 LSB bit System for obtaining correct byte addresses by XOR-ING 2 LSB bit

1983-09-27

1995-03-14

Lall, Parshotam S.

Boots, shoes, and leggings

395425, 3642604, 3642609, 3642395, 3642526, 3642558, G06F 700

Patent

active

053983289

ABSTRACT:
A method and apparatus for enabling a computer to run using either a Big Endian or Little Endian architecture is provided. The method and apparatus use the fact that XORing the lower two bits of a byte address in one architecture with a binary 3 converts that byte address to the equivalent byte address in the other architecture. The conversion method and apparatus is implemented in hardware by setting a bit in a status register indicating a Big Endian or Little Endian architecture in conjunction with an XOR gate which couples the byte address to binary 3. The conversion method and apparatus is implemented in software by scanning the instructions of the input for load and store instructions. The software modifies the instructions by taking the contents of the register and XORing the two least significant bits of the byte address with a binary 3.

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Kirrman; "Data Format and Bus Compatibility in Multiprocessors"; IEEE Micro Aug. 1983, pp. 32-47.
David V. James; "Multiplexed Buses; The Erdian Wars Continue"; IEEE Jun. 1990 pp. 9-20.

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