System for memory unit receiving pseudo-random delay signal oper

Details System for memory unit receiving pseudo-random delay signal oper System for memory unit receiving pseudo-random delay signal oper

1995-06-30

1998-03-17

Lee, Thomas C.

Boots, shoes, and leggings

395800, 395552, 395556, 395559, 3642328, 364270, G06F 1300

Patent

active

057297665

ABSTRACT:
This invention discloses a microprocessor device comprising an execution unit which is governed by a master clock signal and a repeatedly programmable master clock divider which is operative to divide the master clock signal. The microprocessor device is operative to execute instructions executed by an existing microprocessor, wherein said instructions being executed in a given number of machine cycles. Furthermore, the microprocessor includes a programmable instruction mapper containing a multiplicity of mapping schemes for controlling the microprocessor apparatus. A tamper-resistant execution device is included operative to execute instructions arriving from an instruction register. The microprocessor device also includes a pseudo-random access delay signal generator which generates a signal for determining the number of clock cycles elapsing from a memory access instruction cycle to actual memory access. Additionally, a method is also included for testing the contents and integrity of a condition signal within a single machine cycle.

REFERENCES:
patent: 3422404 (1969-01-01), Ferguson
patent: 4399435 (1983-08-01), Urabe
patent: 4584665 (1986-04-01), Vrielink
patent: 4661902 (1987-04-01), Hochsprung et al.
patent: 4785416 (1988-11-01), Stringer
patent: 4827476 (1989-05-01), Garcia
patent: 4851995 (1989-07-01), Hsu et al.
patent: 4947411 (1990-08-01), Taketora et al.
patent: 5115503 (1992-05-01), Durkin
patent: 5125083 (1992-06-01), Fite et al.
patent: 5274796 (1993-12-01), Conner
patent: 5276856 (1994-01-01), Norsworthy et al.
patent: 5301306 (1994-04-01), Plog
patent: 5301356 (1994-04-01), Bodin et al.
patent: 5309561 (1994-05-01), Overhouse et al.
patent: 5311483 (1994-05-01), Takasugi
patent: 5325430 (1994-06-01), Smyth et al.
patent: 5329467 (1994-07-01), Nagamune et al.
patent: 5428746 (1995-06-01), Dalrymple
DS80C320 High-Speed Micro, Dallas Semiconductor.
NEC Electronics Inc. Preliminary Information, V30 PD70116 High-Performance 16-Bit Microprocessor, May 1985, pp. 1-43.
IBM Technical Disclosure Bulletin, vol. 19, No. 12, May 1977, Armonk, US, p. 4529 XP002023744; Lang, et al., "Fault-tolerant Branch on Value Instruction".
New Electronics. Incorporating electronics Today, vol. 21, No. 3, Mar. 1988, London, UK, pp. 47-48, 50, XP000005612; Sweetman D: "Preventing Malfunctions of Microprocessor-Based Equipment".
Proceedings of the Nat'l Aerospace & Electronics Conf. (NAECON), Dayton, May 24-28, 1993, vol. 1 of 2, 24 May 1993, Institute of Electrical & Electronics Engineers, pp. 129-136, XP00041941; Finley, et al., "Realtime Avionics Processor Emulators".

Affiliated with

Also associated with

Rating

System for memory unit receiving pseudo-random delay signal oper does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System for memory unit receiving pseudo-random delay signal oper, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System for memory unit receiving pseudo-random delay signal oper will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-967676