System for masking execution ready signal during unsettled perio

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3642318, 3642613, 3642615, 3642618, 364DIG1, 36494834, 364938, 3649381, 395800, G06F 1300

Patent

active

051858690

ABSTRACT:
An improved microprocessor in which distribance of a pipeline processing flow caused by a conditional branch instruction is suppressed. The microprocessor includes an instruction decoder unit having a precedent decoding function in which at least one instruction subsequent to a conditional branch instruction or an instruction at a branch destination address is decoded in advance during a branch condition unsettled period. A register queue temporarily stores the decoded instructions and a mask control unit responds to the decoder unit by masking a ready state for execution of at least one decoded instruction.

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