Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
1999-04-14
2001-01-30
Monin, Jr., Donald L. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C257S048000, C257S788000, C257S790000
Reexamination Certificate
active
06181017
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to chip scale packages and more particularly to a method and system for marking the chip scale package.
BACKGROUND OF THE INVENTION
Chip-scale packages are used in a variety of semiconductor applications. Chip-scale packages typically include a semiconductor die, or chip, mounted on a substrate. The active area of the semiconductor die includes the circuitry used to perform the desired functions. As their name suggests, chip-scale packages are on the order of the size of a semiconductor die contained within the package.
In order to designate the manufacturer, part type, and other information, the chip-scale packages are typically marked. Because of the amount of information carried in the marking and the size of a chip-scale package, the characters used in the mark are typically relatively fine. Typically, a laser is used to cut into a portion of the silicon on the exposed portion of the die. Thus, a user is able to read information on the chip-scale package relating to the manufacturer, the part type, and other information relating to the device.
One problem with chip-scale devices is damage due to electrostatic charging. When contact is made to the chip-scale package, the electrostatically induced charge may cause a spark. The spark may pass through a substantial portion of the semiconductor die, damaging the active area of the semiconductor die and causing failures in the chip-scale package.
Recently, a mechanism for reducing the damage induced by electrostatic sparking has been discovered. A nonconductive coating, such as an electrophoretic coating, is applied to the semiconductor die of the chip-scale package. In order to maintain the small size of the chip-scale package, the coating is applied in a thin layer. With the exception of the surface of the die which will contact the substrate, the coating substantially covers the semiconductor die. Once the semiconductor die is attached to the substrate, the chip-scale package has a reduced tendency to spark due to electrostatic charging. Thus, the failures due to sparking are reduced.
Although failures are reduced, conventional methods of marking of the chip-scale package are problematic. Conventional laser marking may destroy portions of the coating. As a result, benefits due to the coating will be lost. Even in an uncoated chip-scale package, laser marking may damage the active area, causing failures in the device. Failures may be caused in the chip-scale package for similar reasons if a conventional method for marking the chip-scale package is used.
Accordingly, what is needed is a system and method for marking a chip-scale package having a thin nonconductive coating. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method and system for marking a chip-scale package. In one aspect, the chip-scale package includes a semiconductor die coupled to a substrate and a first coating. The semiconductor die has an exposed portion substantially surrounded by a first coating. In this aspect, the method and system comprise applying a second coating to a first portion of the first coating and marking the second coating. The first coating is not completely penetrated by the marking. In a second aspect, the method and system comprise providing a chip-scale package. In this aspect, the method and system comprise providing a substrate, providing a semiconductor die coupled to a substrate, and providing a first coating. The semiconductor die has an exposed portion. The exposed portion is substantially surrounded by the first coating. In this aspect, the method and system further comprise providing a second coating substantially covering a first portion of the first coating. The second coating has a plurality of markings therein. The first coating is not completely penetrated by the plurality of markings.
According to the system and method disclosed herein, the present invention allows a chip-scale package to carry information to a user while having reduced damage due to sparking from electrostatic charging.
REFERENCES:
patent: 5688573 (1995-11-01), Goeb et al.
patent: 3-093239 (1991-04-01), None
patent: 3293063 (1991-12-01), None
Blish II Richard C.
Hatchard Colin
Yim Daniel
Advanced Micro Devices , Inc.
Monin, Jr. Donald L.
Pham Hoai
Sawyer Law Group LLP
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