Boots – shoes – and leggings
Patent
1991-03-25
1992-05-19
Lee, Thomas C.
Boots, shoes, and leggings
3642426, 3642428, 3642429, 36424291, 364254, 3642543, 364DIG1, G06F 946
Patent
active
051155079
ABSTRACT:
The management of the priorities of access to a memory is characterized in that each request generator module (DP,GP) separately formulates the requests for access to a single word (DPREQ1, GPREQ1) and the requests for access to a plurality of words (DPREQN, GPREQN); differing priorities (REGA, REGB, REGC, REGD) may then be allocated (VALREG) to each type of request. Advantageously the requests for a single word are arbitrated by a first module which transmits a selected request to a second module.
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patent: 3925766 (1975-12-01), Bardotti et al.
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patent: 4493036 (1985-01-01), Boudreau et al.
patent: 4755938 (1988-07-01), Takahashi et al.
patent: 4788640 (1988-11-01), Hansen
Communication from the European Patent Office dated Feb. 21, 1989 in EP8802954.9, a corresponding application.
Communication from the European Patent Office dated Feb. 2, 1989 in a corresponding application.
Siddique "100-MHz DRAM Controller Sparks Multiprocessor Designs", Electronic Design, Sep. 18, 1986, pp. 138-141.
Amos et al., "Dynamic Storage Priority Control", IBM TDB vol. 20, No. 10, Mar. 1978, p. 4033.
Lee Thomas C.
Rhyne Lesley
Treat William M.
U.S. Philips Corp.
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