System for maintaining low bit error rate in a starcoupled netwo

Details System for maintaining low bit error rate in a starcoupled netwo System for maintaining low bit error rate in a starcoupled netwo

1986-07-23

1989-08-08

Griffin, Robert L.

Pulse or digital communications

Repeaters

Testing

375 36, 330297, H04B 336, H04L 2520

Patent

active

048560235

ABSTRACT:
A data process system has a plurality of stations or terminals linked to a star coupler over cables comprising separate sending and receiving transmission lines, the cable shield being connected to system ground. To minimize bit error rate when a station is powered down, the transmitting differential amplifier at each terminal station is connected between a bias voltage and a virtual ground created by a pair of diodes connected in parallel, their anodes being connected to a voltage source through a current limiting resistor, the cathode of one diode being connected to system ground, the cathode of the other diode being connected to one side of the transmitting amplifier to define the virtual ground. To further enhance noise rejection, a balanced differential network is connected to the outputs of a transistor pair at the amplifier output to the differential wire transmission line. The network comprises a resistor and diode connected in series between each transistor's emitter output and the amplifier bias voltage source, the combined resistance and dynamic impedance of each portion of the balanced differential network being equal. At the receiver end of the star coupler cabinet, a series resistor network is coupled from a bias voltage source for a differential receiver amplifier to the system ground. The receiver amplifier has two input transistors; the resistor network includes a resistor coupled across the transistor inputs of a resistance matched to the characteristic impedance of the cable; two additional resistors are connected in series between the ends of this resistor and the inputs to the amplifier transistors to define a relatively high offset voltage across the input to the receiver amplifier.

REFERENCES:
patent: 3633165 (1972-01-01), Gilbert
patent: 3827026 (1974-07-01), Viswanathan
patent: 3855419 (1974-12-01), Hurford
patent: 4417334 (1983-11-01), Gunderson et al.
patent: 4507793 (1985-05-01), Adams
patent: 4561091 (1985-12-01), Scholl et al.
patent: 4569059 (1986-02-01), Fish

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