Electric heating – Heating devices – Combined with container – enclosure – or support for material...
Reexamination Certificate
2001-07-12
2002-06-18
Walberg, Teresa (Department: 3742)
Electric heating
Heating devices
Combined with container, enclosure, or support for material...
C219S405000, C219S411000, C392S416000, C118S724000, C118S725000, C118S050100
Reexamination Certificate
active
06407368
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention broadly relates to equipment for manufacturing semiconductor devices, such as integrated circuits, and deals more particularly with maintaining a flat temperature profile at all levels of a low-pressure vertical furnace.
2. Description of the Related Art
In connection with processes used to manufacture semiconductor deices, such as integrated circuits, numerous process steps are carried out in a controlled environment at elevated temperatures. Such processes include oxidation, diffusion, chemical vapor deposition and annealing. In order to realize elevated processing temperatures, semiconductor wafers are processed in an evacuation chamber, typically in a form of a quartz tube that is housed within a semiconductor furnace.
The most common type of semiconductor furnaces is the so-called “hot wall” electric type that facilitates batch processing of semiconductor wafers. Furthermore, hot wall electric furnaces exhibit excellent temperature stability and precise temperature control. Modern hot wall diffusion furnaces are capable of controlling temperatures over the range of 300° C. to 1200° C.
The processing of semiconductor wafers and other microelectronic components has become of great economic significance due to the large volume of such circuits and components being produced and the significant value associated with them. Competitive pressures have driven dramatic changes in production. Among the most dramatic changes is the reduction in size of the various features of the circuits and components that make up the transistors and other devices being formed. This reduction in feature size has been driven by the need to achieve greater levels of integration, more sophisticated and complex circuits, and reduction in production costs by, for example, obtaining more circuits on each semiconductor wafer or other substrate being processed.
Even though feature sizes used in integrated circuits and other microelectronic components have decreased dramatically, additional reductions are continuously being pursued. As feature size decreases, the importance of accurate temperature control during processing increases to even a greater degree. The temperature at which semiconductor wafers and other substrates are processed has a first order effect on the diffusion of dopants, deposition of materials or other thermal processes being performed. Thus, it is important to have processing equipment that can achieve accurate temperature control to meet desired thermal processing specifications.
Various temperature control problems must be addressed by a thermal process control system if it is to meet the increasingly stringent requirements of the microelectronic circuit manufacturing industry. For example, each wafer in a batch should be subject to the same temperature conditions over the entire thermal processing cycle. Left uncontrolled, temperature variations occur between the wafers positioned near the ends of an array of wafers held within the processing furnace when compared to the wafers disposed at mid-portions of the furnace. There may also be other less predictable variations from wafer to wafer, such as along the array of wafers contained within the processing array.
A still further temperature control problem is associated with temperature variations that occur across the width of an individual wafer or other workpiece being processed. Heat from heating elements disposed about peripheral edges of the work pieces is radiated through the processing vessel. Variations can occur with regard to the heat gain experienced by the peripheral edges of the wafer as compared to the interior areas of the wafer. Variations in the degree of radiant heat transfer and radiant shadowing, which occurs from wafer to wafer further, exacerbates this intra-wafer problem.
A tilted temperature profile from 770° C. to 730° C. from the top of the furnace to the bottom of the furnace is an intrinsic characteristic of LP vertical furnaces. Top and bottom refer to the boat stack with the bottom being nearest the source of heat. This characteristic is due to the loading effect and reaction gas depletion at the top site close to the pumping line.
Reaction gas depletion at the top site is due to the confinement of the bottom site injector arrangement near the pedestal.
Some devices with gate implant (N+/P+) after gate poly deposition are very sensitive to the following low-pressure furnace thermal process, such as spacer deposition, because of the further thermal-drive dopant. U.S. Pat. No. 6,214,715B1, entitled “Method for Fabricating a Self Aligned Contact Which Eliminates the Key Hole Problem Using a Two Step Spacer Deposition” issued on Apr. 10, 2001 to a common assignee describes a two-step spacer deposition and is incorporated herein by reference.
Another problem with the tilted temperature profile in these furnaces, causes the VTP/N, (Vapor Transfer Polymerization) or other parameters variation on products experiencing different thermal budget at different boat positions is the furnace.
U.S. Pat. No. 6,168,427B1 entitled “Apparatus for Guiding the Removal of a Processing Tube from a Semiconductor Furnace” issued on Jan. 2, 2001 and assigned to a common assignee, teaches an apparatus for removing the quartz tube from the furnace for routine maintenance. This apparatus facilitates the removal of the quartz tube from the furnace that precludes or substantially reduces the possibility of the tube coming in contact with the sidewalls of the furnace during the removal process.
It is an advantage of the present invention to maintain a uniform temperature profile along the height of the boat support in the vertical furnace.
It is a further advantage of the present invention to reduce wafer scrap due to temperature variations during the processes performed in the semiconductor furnace.
It is still a further advantage of the present invention to increase the capacity of the furnace by allowing more boat positions in the furnace.
These and other advantages will become apparent in the following drawings and detailed description of the preferred embodiment.
SUMMARY OF THE INVENTION
A system for maintains a flat zone temperature profile in a low-pressure vertical furnace for a temperature-sensitive process, the system having a platform with a central aperture. A pedestal adapted to extend through the central aperture having at least one wafer boat axially mounted thereon.
A processing tube having an open end mounted on the platform surrounding the central aperture.
A multiple wall inner tube having a first inner tube is mounted within the outer bell and spaced therefrom. The first inner tube extends from the platform to proximately the enclosed end of the processing tube. A second inner tube is mounted in a radially spaced relationship within the first inner tube. Again the spacing is on the order of millimeters. The second inner tube extends a predetermined height in the first inner tube.
A plurality of spacers are positioned between the first and second inner tubes forming an unitary or integral structure. The spacers maintaining the tubes radially spaced apart to provide flow passageways between the first and second inner tubes. The multiple wall inner tube has an internal diameter adapted to receive at least one wafer boat.
A plurality of igniters substantially equally spaced on the pedestal and adapted to supply heat to the passageways and the inner diameter of the second inner tube.
A controller operatively connected to the igniters and is responsive to a predetermined temperature profile for maintaining the temperature of heat from the igniters surrounding the boats.
REFERENCES:
patent: 5482558 (1996-01-01), Watanabe et al.
patent: 5622639 (1997-04-01), Kitayama et al.
Hsu Chun-Keng
Lee Chao-Lin
Lin Chun-Chih
Lin Sung-Chieh
Fuqua Shawntina
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
Walberg Teresa
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