System for limiting if variation in phase locked loops

Details System for limiting if variation in phase locked loops System for limiting if variation in phase locked loops

1999-12-07

2001-03-06

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S011000, C331S016000, C331S018000, C331S022000, C331S025000, C327S156000, C455S260000

Reexamination Certificate

active

06198354

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to phase locked loops, and more particularly, to a system for limiting intermediate frequency variation in multiple conversion phase locked loops.
BACKGROUND ART
Manufacturers of electronic equipment typically include phase locked loop synthesizers as components of many electronic products and systems. For example, phase locked loop synthesizers having voltage controlled oscillators are widely used as digital tuners for communication transmitters and receivers. They are also commonly used in controllers for variable speed motors.
A phase locked loop (hereinafter, referred to as a PLL) is an automatic control circuit for processing an output oscillation frequency which is completely synchronized with, or the same frequency as, the frequency of an input signal or a reference oscillator output signal. Generally, the PLL includes a phase comparator (or a phase detector), a low pass filter, and a voltage controlled oscillator, combined to form a feedback loop.
Typical PLL synthesizers are either single conversion PLLs or multiple conversion PLLs. In the operation of a single conversion PLL, a voltage controlled oscillator (VCO) at frequency fo is divided in frequency by N1, a fixed reference oscillator at frequency frosc is divided in frequency by Nr, and the divided frequencies are mixed together to produce an error signal which is driven to zero frequency (“DC”) when the PLL is locked. Thus, when the loop is locked, frosc/Nr=fo/N1 and,
fo=N1/Nr·frosc  (1)
A loop filter amplifies and filters the error signal. The output of the loop filter controls the frequency of the VCO through its voltage control input, closing and locking the PLL.
The phase noise generated by a PLL synthesizer comes from 3 sources: the reference oscillator, the VCO and the PLL electronics. The primary problem with single conversion PLLs is that the phase noise spectrum at the VCO output due to the PLL electronics So(f) is given by,
So=K·(fo/fss)2  (2)
where minimum frequency step size fss of the synthesizer due to changes in the dividers and K is a proportionality constant. Thus, the phase noise spectrum due to PLL electronics noise gets larger as the step size gets smaller, limiting the ability of single conversion PLLs to generate high frequencies with very small step sizes.
A multiple conversion PLL operates in the much the same manner. As before, a fixed reference oscillator at frequency frosc is divided in frequency by Nr. The Nr divider generates an output frequency fr. Thus, the reference oscillator frequency if given by,
frosc=Nrfr  (3)
Also as before, divider N1 divides frequency fo and mixes this in a first mixer with frequency fr. In this case however, the output of this mixer is not zero frequency, but an intermediate frequency (IF) f1. A divider N2 outputs fo/N2, and this is mixed in a second mixer with f1 to produce a second IF f2. This process is repeated as many times as necessary using dividers N3 to Nn until the final mixer output is used to lock the PLL. The output frequency of this multiple conversion PLL is given by,
fo=frosc/(N1−1±N2−1 . . . . ±Nn±1)·Nr  (4)
where the ±s are determined by the mixer sideband utilized for each mixer. A polarity switch is necessary because the sideband choices also determine the sense of the phase error in the final mixer output. Therefore, the minimum step fsm size of a multiple conversion PLL, assuming fr>>f1>>f2>> . . . fn−1, is given by,
fsm{tilde over (=)}N1fo/Nn2  (5)
Thus, N1 can be chosen independently of the minimum step size because of the extra parameter Nn. This means the phase noise spectrum multiplication factor, which is still given by N12 (relative to the output at fr), is decoupled from the step size in multiple conversion PLLs. This decoupling is the main advantage of multiple conversion PLLs, i.e., fr can be chosen to minimize the phase noise, while the extra conversions supply as much resolution as needed.
There is a problem, however, in utilizing multiple conversion PLLs when fo is to operate over a large range. The problem is that the IFs can vary widely as fo is changed without proper IF management. If the IFs vary widely, spurs from unwanted mixing products cannot be properly filtered to keep them out of the VCO output and step size can vary widely over the output range. For proper PLL operation, the IFs need to be as low as possible and simultaneously much greater than the loop bandwidth (BL) of the PLL for all operating frequencies fo.
In order to get around the frequency range limitations of conventional multiple conversion PLLs, makers of electronic equipment utilize custom frequency crystal oscillators and multiplier chains to generate the desired frequencies. Unfortunately, custom frequency crystals for these oscillators require approximately six months to procure. Manufactures are forced to stock large quantities of these crystals in advance at additional expense for commercial applications to enable oscillator fabrication in a short period of time.
Therefore, there is a need to eliminate the extra complexity and expense of using custom frequency crystal oscillators by improving the performance of multiple conversion PLLs. There is also a need to improve the frequency output range of multiple conversion PLLs, while reducing output noise by limiting IF variation.
SUMMARY OF THE INVENTION
It is, therefore, an object of the invention to provide an improved and reliable multiple conversion PLL. Another object of the invention is to limit IF variation in multiple conversion PLLs.
In one aspect of the invention, an apparatus for limiting intermediate frequency variation in a multiple conversion phase locked loop includes a reference oscillator and a voltage controlled oscillator (VCO). The reference oscillator generates a first reference frequency, while the VCO generates an output frequency. The output frequency is divided by a first VCO divider and mixed with the first reference frequency to generate a first intermediate frequency. A second VCO divider also divides the output frequency and mixes it with the first intermediate frequency to generate a second intermediate frequency, which is filtered and used to control the VCO. An algorithm processor generates the division constants of the first and second VCO dividers as a function of the reference frequency and the output frequency to limit intermediate frequency variation.
The present invention thus achieves an improved multiple conversion PLL. The present invention is advantageous in that it extends the useful frequency range of a convention PLL by limiting IF variation.
Additional advantages and features of the present invention will become apparent from the description that follows, and may be realized by means of the instrumentalities and combinations particularly pointed out in the appended claims, taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
In order that the invention may be well understood, there will now be described some embodiments thereof, given by way of example, reference being made to the accompanying drawings, in which:
FIG. 1
is a perspective view of a satellite phase locked loop system according to one embodiment of the present invention; and
FIG. 2
is a block diagram of a system for limiting IF variation in phase locked loops according to one embodiment of the present invention.


REFERENCES:
patent: 4303893 (1981-12-01), Goldberg

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