System for independent cache-to-cache transfer

Details System for independent cache-to-cache transfer System for independent cache-to-cache transfer

1982-05-27

1985-03-05

Thomas, James D.

Boots, shoes, and leggings

G06F 1300, G06F 1516

Patent

active

045034974

ABSTRACT:
The disclosure provides a plurality of embodiments for controlling the bus paths for a line of data from any cache in a multiprocessing system (MP) to any requesting cache or I/O channel processor in the MP. The data transfers can occur in parallel among plural CPU caches, channel processors and main storage (MS) sections using crosspoint switches in a manner which utilizes the high circuit count of LSI modules without substantially utilizing the module I/O pin count to enable MP structures to contain more CPUs than could be contained with conventional bussing.

REFERENCES:
patent: 3735360 (1973-05-01), Anderson et al.
patent: 3806888 (1974-04-01), Brickman et al.
patent: 4032899 (1977-06-01), Jenny et al.
patent: 4394731 (1983-06-01), Flusche et al.
patent: 4410944 (1983-10-01), Kronies

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