Pulse or digital communications – Pulse width modulation
Reexamination Certificate
1998-07-10
2001-10-30
Chin, Stephen (Department: 2734)
Pulse or digital communications
Pulse width modulation
C318S268000
Reexamination Certificate
active
06310912
ABSTRACT:
FIELD OF APPLICATION OF THE INVENTION
The present invention relates to techniques for driving a generic resistor-inductor (R-L) actuator through an output power stage having a so-called bridge configuration, and, more particularly, to a technique for driving an output bridge stage in a pulse-width modulation (PWM) mode, thus partitioning the voltage delivered to the actuator and thereby controlling the current flowing through it.
BACKGROUND OF THE INVENTION
The control signal of a PWM driving system may, according to recently developed techniques, be generated by a circuit that transforms a predefined N-bit digital value permanently stored in a nonvolatile memory, that can be scanned at a variable clock speed, into a digital signal. The digital signal will have an amplitude compatible with the input requirements of the output power stage, and the duty-cycle is proportional to the N-bit digital value read from the memory.
A conversion system of this nature where N=8 is described in the European patent application No. 96830295.0, filed on May 22, 1996, and assigned to the assignee of the present invention. A conversion system as those mentioned above and shown in
FIG. 1
is based on comparing the input BYTE (N=8) containing the value to be converted with the state of an 8-bit counter functioning in a continuous up/down mode.
A sample signal is input to the input register
10
acting as the SL latch with appropriate circuit input signal from newsamp. The input register output is then input to the comparator circuit
14
which receives another signal from up/down counter circuit
16
. This, in turn, receives the clock signal and outputs a signal to the comparator circuit
14
. Another output from the comparator circuit is input into logic circuit
18
together with output EN from up/down counter circuit
16
into the clock input for the FF
2
circuit
12
. This acts as a set circuit with an output PWMOUT. The up/down counter circuit receives an end of counter output into the FF
1
circuit
20
, which also has an output back to the counter circuit. An initialized circuit
22
inputs a reset and set signal to respective FF
1
and FF
2
circuits.
The above referred conversion circuit is depicted in FIG.
2
. By referring to
FIGS. 1 and 2
, the sample (N=8 BYTE) to be converted is synchronously loaded in the SL register to prevent sample updating during its conversion. The comparator COMP generates a clock impulse for the toggle bistable circuit FF
2
each time the counter CNT state equals the value of the sample to be converted. This generates a signal PWMOUT whose duty-cycle varies proportionally with the input sample value and symmetrically with respect to the maximum counting value.
However, as it may be observed, the unitary increment (highlighted in an exaggerated manner in
FIG. 2
) of the input sample value to be converted results in a double and symmetric decrement of the output duty-cycle. For example, going from a sample value 188 to a sample value 189 results in a duty-cycle decrement as depicted by the dashed line of FIG.
2
.
In driving an output bridge stage by controlling the current in a Phase Shift Modulation mode, according to the method disclosed in the European patent application No. 95830371.1, filed Aug. 3, 1995, and assigned to the assignee of the present invention, two digital values must be converted, one for each half-bridge, having a symmetric value about 2
N
/2. In a driving system of this kind, where to a unit increment of the digital signal forced in a half-bridge corresponds a unit decrement of the digital signal that is simultaneously forced in the other half-bridge to maintain symmetry. A double duty-cycle differential increment is produced if compared to the case of a half-bridge output stage.
SUMMARY OF THE INVENTION
An object of the present invention is a circuit that improves the definition of the above mentioned conversion process by increasing from N to N+2 bits the dimension of the input datum, thereby improving the control of the current in the actuator without incrementing the size (number of bits) of the digital comparator. The system of the present invention avoids the prior art augmented duty-cycle increments for unitary variations of the value of input samples in driving a full-bridge.
The invention is effective in “monophase” systems employing a single full-bridge output stage, as well as in multi-phase systems using a plurality of full-bridge output stages. The invention may be used, for example, in certain driving systems for multi-phase brushless electric motors for permitting a dynamic control of the driving mode.
REFERENCES:
patent: 4138632 (1979-02-01), Pauwels et al.
patent: 4590457 (1986-05-01), Amir
patent: 4894598 (1990-01-01), Daggett
patent: 5103462 (1992-04-01), Elle et al.
patent: 5488487 (1996-01-01), Ojima et al.
patent: 5933344 (1999-08-01), Mitsuishi et al.
patent: 0760552 A1 (1995-08-01), None
Miguel F. escalante G, Pulse Width Modulated Inverter with Current Control, IEEE 1995, pp. 74-79.*
J. Brett and R. M. Nelms, Speed Control of a Brushless DC Motor Using Pulse Density Modulation and MCT's, IEEE 1994, pp. 356-362.
Galbiati Ezio
Maiocchi Giuseppe
Al-Beshrawi Tony
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Chin Stephen
Galanthay Theodore E.
STMicroelectronics S.r.l.
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