System for implementing write, initialization, and reset in a me

Details System for implementing write, initialization, and reset in a me System for implementing write, initialization, and reset in a me

1995-12-20

1998-09-01

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523001, 36523005, 36518908, G11C 700, G11C 800

Patent

active

058020039

ABSTRACT:
A system is provided for providing functional, initialization and reset access to a plurality of memory cells of a memory array, using a single cell write port and a single cell read port. In addition to functional address and data buses, initialization address and data buses are provided. The invention is disclosed in association with a field-programmable memory array having multiple sub-arrays therein. The address units for each sub-array are provided to programmably provide address information to the wordlines of each sub-array from an initialization address bus or a functional address bus. Similarly, readhead and writehead circuits within each sub-array are also programmable to propagate data between initialization or functional data buses and the memory cells of the sub-array. The address units, readheads, and writeheads are all responsive to a dominant reset signal to reset the associated cells. An initialization select bus is disclosed for selecting a given sub-array of the multiple sub-arrays for the initialization function. A programming or configuration system for the field-programmable memory array is disclosed with additional units for operating the address and data buses, address units, readheads, writeheads, and the initialization buses.

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