System for identifying a primary processor and non-primary proce

Details System for identifying a primary processor and non-primary proce System for identifying a primary processor and non-primary proce

1996-07-12

1997-08-05

Lee, Thomas C.

395823, 395828, 395829, 395284, G06F 1300

Patent

active

056551495

ABSTRACT:
An integrated network switch system which can uniquely and consistently detect and designate each processor on a bus without the relative position information, and allow a dynamic reallocation of the processors according to their designations. A pseudo code residing within each processor is implemented to effect the detecting and designating operation of the integrated network switch system. Additionally, a shared RAM and a hardware register which are made accessible to all processors on the bus at a fixed location are used to assist the designating operation of the system, and each processor's memory is used to assist the delaying operation of the system. This assures that tasks among the processors are distributed according to their designations, and that each of the processors can be removed or added without any hard coded configuration.

REFERENCES:
patent: 4688212 (1987-08-01), MacGinitie et al.
patent: 5204669 (1993-04-01), Dorfe et al.
patent: 5321813 (1994-06-01), McMillen et al.
patent: 5444695 (1995-08-01), Copley et al.
patent: 5491788 (1996-02-01), Cepulis et al.

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