Modulators – Phase shift keying modulator or quadrature amplitude modulator
Reexamination Certificate
2003-04-21
2004-08-10
Mis, David (Department: 2817)
Modulators
Phase shift keying modulator or quadrature amplitude modulator
C332S105000, C375S308000
Reexamination Certificate
active
06774740
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to phase modulators, and more particularly, to a highly linear architecture for direct phase modulation of a phase-locked loop.
BACKGROUND OF THE INVENTION
Phase modulation schemes—techniques that convey information using the phase of the carrier signal—are effective communication methods. A popular phase modulation scheme is quaternary phase shift keying (QPSK).
FIG. 1
shows a constellation diagram that illustrates how QPSK maps two-bit digital data to one of four offsets.
FIG. 2
shows a typical QPSK (or I/Q) modulator used to generate a phase-modulated signal. This technique relies on orthogonal signal vectors to realize the phase offsets—an inherently linear technique, since it depends solely on the matching of these orthogonal signals.
However, the typical I/Q modulator requires several power-consuming circuits to generate the orthogonal signals. It would therefore be advantageous to have a low-power highly linear phase modulator that is highly integrated.
SUMMARY OF THE INVENTION
The present invention comprises a very efficient system for highly-linear phase modulation. The system includes important calibration circuitry for direct modulation of the VCO used in a phase-locked loop to synthesize a radio frequency carrier signal.
In one embodiment, apparatus is provided for linear phase modulation utilizing a phase-locked loop (PLL). The apparatus includes a PLL utilizing fractional N synthesis to realize a non-integer divide value. A two-port voltage-controlled oscillator includes a first port controlled by the phase-locked loop and a second port accessed for direct modulation. A second input to the fractional-N phase-locked loop is provided to remove the modulation introduced at the second port. Lastly, a calibration loop is provided wherein a frequency offset applied at the second port is adjusted until it cancels the effects of a known frequency offset introduced to the fractional-N phase-locked loop.
In one embodiment, apparatus is provided for linear phase modulation utilizing a phase-locked loop. The apparatus comprises a phase-locked loop (PLL), utilizing fractional N synthesis, where an N counter in a feedback loop is pseudo-randomly switched between integer values to realize a non-integer divide value. The apparatus also comprises a two-port voltage-controlled oscillator, the first port controlled by the phase-locked loop and a second port accessed for direct modulation. In one embodiment, the second port utilizes MOSFET capacitors that present an effective capacitance to the voltage-controlled oscillator equal to the time-averaged value of two capacitances, the value linearly changing with the applied control voltage. A second input to the fractional-N phase-locked loop is provided to remove the phase modulation introduced at the voltage-controlled oscillator. Lastly, a calibration loop is provided wherein a frequency offset applied at the voltage-controlled oscillator's second port is adjusted until it cancels the effects of a known frequency offset introduced to the fractional-N phase-locked loop.
In another embodiment included in the present invention, apparatus is provided for calibration of a phase-locked loop used for phase modulation. The apparatus comprises a sampling circuit that stores the control voltage of the phase-locked loop. The control voltage indicates the nominal operating point of the loop. A window comparator is provided that compares the sampled control voltage and nominal operating point of the loop to the present control voltage after modulation is applied. A control network accepts the output of the window comparator and properly sets a memory register used to control a digital-to-analog converter. Lastly, a digital-to-analog converter generates the reference level for a second digital-to-analog converter for inputting digital phase modulation data.
In another embodiment included in the present invention, a method is provided for calibration of a phase-locked loop used for phase modulation. The method comprises steps of sampling the control voltage when the phase-locked loop is phase locked and operating normally, altering the data input applied to the N counter of the phase-locked loop so as to shift its operating frequency, stepping the data input applied to the phase modulation input that directly connects to the second control port of the voltage-controlled oscillator of the phase-locked loop so as to achieve a frequency shift, monitoring the control voltage of the phase-locked loop and comparing it to the sampled control voltage corresponding to the nominal operating point of the phase-locked loop and measured before the frequency offset data was applied, and adjusting the scaling factor or reference level associated with the digital-to-analog converter used to convert the phase modulation digital input to an analog signal until the frequency shift introduced by way of the phase modulation input and voltage-controlled oscillator cancels the programmed frequency offset entered by way of the N counter of the phase-locked loop as measured by the window comparator, which compares the sampled and current values of the phase-locked loop's control voltage.
In another embodiment included in the present invention, a method is provided for sampling the control voltage of a phase-locked loop using a digital-to-analog converter. The method comprises steps of establishing an adjustable reference using a pair of resistors, connected to a fixed bias current source and a variable current source, comparing the adjustable reference to the control voltage to be duplicated, and adjusting the digital input to a digital-to-analog converter, used to create the variable current source that offsets the adjustable reference, until the reference matches the control voltage to be sampled.
REFERENCES:
patent: 5818303 (1998-10-01), Oishi et al.
Mis David
Sequoia Communications Corp.
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