System for high-speed synchronization across clock domains

Details System for high-speed synchronization across clock domains System for high-speed synchronization across clock domains

1994-12-22

1996-01-23

Chin, Stephen

Pulse or digital communications

Synchronizers

375371, 375363, 375373, H04L 700

Patent

active

054870925

ABSTRACT:
A high-performance clock synchronizer for transferring digital data across the asynchronous boundary between two independent clock domains operating at hardware-limited clock speeds. The external clock signal latches each incoming data word in a boundary register. An external clock divider produces several prolonged clock signals synchronized to the external clock signal for use in distributing the incoming data words into a bank of several external buffer registers, where each word stabilizes for more than one full internal clock interval before transfer across the asynchronous boundary to a bank of corresponding internal buffer registers synchronized to the internal clock signal. A special logic inserts and deletes pad words to equalize data flow rates. Another special logic reassembles the data words in proper sequence after transfer to the internal buffer register bank. Flag latches are used to avoid asynchronous sampling of more than one bit in each data word.

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R. E. Fuhs et al., "Passing Data Stream Across Asynchronous Clock Domains in Scalable Coherent Interface Bus", IBM Technical Disclosure Bulletin, vo. 36, No. 11, Nov. 1993, kpp, 373-375.

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