System for high speed data tranmission

Pulse or digital communications – Repeaters – Testing

Patent

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Details

332100, 329300, 375 88, 375 62, H04L 2710

Patent

active

051054442

ABSTRACT:
A modulator (14) and a demodulator (30) cooperate in a system (10) to communicate data at a high data rate using a pulse frequency modulation scheme (PFM). The modulator (14) receives data symbols in a FIFO memory (72) and applies the data symbols, after an adjustable delay, to a variable frequency oscillator (74) to control the frequency of a carrier waveform (16) generated by the oscillator (74). Circuits (76, 78, 98) monitor the carrier waveform (16) and couple to the FIFO memory (72) to control the advancing of data to the oscillator (74). Consequently, the carrir waveform (16) is capable of changing frequency at each half-cycle of the carrier waveform (16), and such changes occur only at zero-crossings of the carrier waveform (16). The carrier waveform (16) is applied through a transmission channel (22) to the demodulator (30). The demodulator (30) includes a comparison circuit (36-42) which produces bipolar signals describing positive and negative half-cycles of the carrier waveform (16). These bipolar signals are de-glitched (96, 98) and applied to start and stop control inputs (52, 54) in respective positive and negative counter circuits (44p, 44n). Each of the counter circuits (44) includes a counter (58) which counts a high speed clock signal supplied by a clock generator (46) during one of the half-cycles to produce a period count that describes the duration of the half-cycle. During a subsequent half-cycle, a translation circuit (60) converts the period count into a amplitude value that describes the data symbol modulated onto the carrier waveform (16), and a resetting circuit (64-68) presets the counter (58) to an initial value.

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