System for handling interrupts in a computer system using asic r

Details System for handling interrupts in a computer system using asic r System for handling interrupts in a computer system using asic r

1996-02-01

1998-09-29

Lee, Thomas C.

395866, 395856, G06F 900, G06F 946

Patent

active

058157336

ABSTRACT:
The present invention provides an interrupt register for handling interrupt requests received from external devices at a common interrupt terminal of a CPU. The invention provides inputs, outputs, and storage means as part of the interrupt register. The interrupt register inputs and outputs are used for communication with both the external devices and CPU to prevent mishandling of the interrupt requests.

REFERENCES:
patent: 5003462 (1991-03-01), Blaner et al.
patent: 5133056 (1992-07-01), Miyamori
patent: 5410708 (1995-04-01), Miyamori
patent: 5481724 (1996-01-01), Heimsoth et al.
patent: 5542076 (1996-07-01), Benson et al.
patent: 5615375 (1997-03-01), Ibusuki et al.
patent: 5630152 (1997-05-01), DeLuca et al.
patent: 5640571 (1997-06-01), Hedges et al.

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