System for guarantee reexecution after interruption by condition

Details System for guarantee reexecution after interruption by condition System for guarantee reexecution after interruption by condition

1990-08-29

1993-05-18

Lee, Thomas C.

Boots, shoes, and leggings

395425, 395800, 3642318, 36494834, 364DIG1, G06F 922, G06F 906

Patent

active

052127796

ABSTRACT:
A data processor which is constructed such that, when writing processing of an operand to external devices is included as the last step processing of a microprogram, by moving only the writing processing to a next pipeline stage, all of external access processings during execution of the microinstruction in the other plural steps are executed in an instruction execution stage, thereby information showing the internal states such as PSW, PC, and the like can be managed in the instruction execution stage alone to facilitate exceptional processing.

REFERENCES:
patent: 4635194 (1987-01-01), Burger et al.
patent: 4648034 (1987-03-01), Heniger
patent: 4777594 (1988-10-01), Jones et al.
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 5043868 (1991-08-01), Kitamura et al.
patent: 5067069 (1991-11-01), Fite et al.
patent: 5084837 (1992-01-01), Matsumoto et al.
Proc. of ICCD 1987, pp. 168-172.

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