System for generating pseudorandom sequences

Cryptography – Communication system using cryptography – Pseudo-random sequence scrambling

Reexamination Certificate

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C380S270000, C370S209000

Reexamination Certificate

active

10046601

ABSTRACT:
A system for generating pseudorandom codes using a register which contains an identification of the code tree leg of the desired code and a counter which outputs a successive binary sequence. The output from the counter is bit-by-bit ANDed with the output of the register, and those outputs are XORed together to output a single bit. As the counter is sequenced, each count results in a different bit that is output from the XOR gate, resulting in the desired code.

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Kung, VLSI Array Processors, pp. 436-438, 1988.
Kung, “VLSI Array Processors”, 1998, pp. 436-438.

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