System for generating memory timing and reducing memory access t

Details System for generating memory timing and reducing memory access t System for generating memory timing and reducing memory access t

1990-11-07

1993-04-13

Clawson, Jr., Joseph E.

Static information storage and retrieval

Addressing

Sync/clocking

365 52, 365 63, 36523003, 365239, G11C 804

Patent

active

052028577

ABSTRACT:
A system for generating memory timing signals and for reducing memory access time includes a plurality of memory modules having an array of memory cells addressable in response to a number of row address select and column address select signals. A row address select signal generator associated with each memory module generates row address signals upon the system receiving a request for access to any memory storage location. At least one memory array selection comparator compares memory address signals with preselected, unique, memory module addresses, for identifying a selected memory module, and for providing a column address signal generator enable signal to the column address select signal generator of the selected memory module. The row address select timing signals enable one or more row address select signals to each memory module prior to the time that the at least one memory array selection comparator identifies the selected memory module and provides the column address select signal generator enable signal to the associated column address signal generator of the selected memory array.

REFERENCES:
patent: 4663735 (1987-05-01), Novak et al.
patent: 4785428 (1988-11-01), Bajwa et al.
patent: 4933910 (1990-06-01), Olson et al.
patent: 4953131 (1990-08-01), Purdham et al.
patent: 5036493 (1991-07-01), Nielsen
patent: 5042013 (1991-08-01), Sato
patent: 5043947 (1991-08-01), Oshima et al.

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