Chemistry: electrical and wave energy – Apparatus – Electrolytic
Reexamination Certificate
2000-03-30
2001-07-17
Gorgos, Kathryn (Department: 1741)
Chemistry: electrical and wave energy
Apparatus
Electrolytic
C134S094100, C134S099100, C134S182000
Reexamination Certificate
active
06261427
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to lithography and specifically to an improved method, apparatus and system for fabricating stencil masks for ion beam and electron beam lithographic systems.
2. Description of the Related Art
Ion and electron beam lithographic systems utilize a stencil mask to pattern a resist coated target. These stencil masks can include a thin membrane which carries the mask pattern. Typically, the stencil mask includes a substrate, and the membrane is an area of reduced thickness on the substrate. The mask pattern can be formed by solid areas and openings in the membrane. The membrane can also include an ion absorbing layer formed of a conductive material deposited on the solid areas of the membrane. The conductivity of the ion absorbing layer can be used to provide a ground path to prevent charge build up on the membrane. In addition, the ion absorbing layer preferably has a high emissivity to facilitate radiative heat removal due to absorption of incident ions.
FIG. 1
schematically illustrates a prior art stencil mask
10
. The stencil mask
10
includes a substrate
12
which has been etched to form a membrane
14
. A mask pattern
16
has been formed on the membrane
14
by etching a desired pattern of openings
18
through the membrane
14
. In addition, an ion absorbing layer
20
has been formed on one side of the membrane
14
on solid areas of the mask pattern
16
. Typically, the substrate
12
and membrane
14
comprise silicon. Other deposited or grown materials, such as SiC, SiN, and BN, can also be used to form portions of the substrate
12
and membrane
14
. A representative thickness for the membrane
14
is from 2-10 &mgr;m.
One prior art process for forming a thin membrane is described in U.S. Pat. No. 5,110,373 entitled “Silicon Membrane With Controlled Stress”. This process includes electrochemically etching a backside of a substrate with a required membrane pattern. A thickness of the membrane is controlled by initially doping the substrate to a required depth with dopants of a predetermined concentration. One aspect of prior art membrane formation processes is that the membrane can be difficult to uniformly etch with the required dimensional accuracy.
In addition, any layers of material added to portions of the membrane, such as the ion absorbing layer, can produce stresses and distortion in the membrane. For example, resist masks and hard masks, required for forming the ion absorbing layer, can stress the membrane. These stresses can distort the mask pattern, and contribute to membrane rupture. Some membrane fabrication processes may also require dry etching and handling of the thin membrane, which can lead to stress-induced distortion, as well as breakage of the membrane.
In view of the foregoing, improved methods are needed for fabricating stencil masks for electron beam and ion beam lithography. The present invention is directed to an improved method for fabricating stencil masks. The method is characterized by reduced complexity and an improved stencil mask.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method, apparatus and system for fabricating stencil masks for electron beam and ion beam lithography are provided. The method, simply stated, comprises: providing a substrate; defining a membrane area by implanting a dopant into a first side of a substrate; defining a mask pattern by etching recesses in the membrane area; and then forming a membrane by etching from a second side of the substrate. With this method the membrane area and mask pattern can be defined on a front side of a standard full thickness silicon wafer, using conventional semiconductor fabrication equipment. Once the membrane area and mask pattern have been defined, the back side of the substrate can be etched to form the membrane and complete the mask pattern.
In an illustrative embodiment, a P− silicon substrate is provided. Initially, an N+ membrane area is defined on the substrate by ion implanting an n-type dopant into the substrate to a selected depth. A TEOS hard mask is then formed on the substrate, and the N+ membrane area is RIE etched with a pattern of recesses to define the mask pattern. Following formation of the recesses, the P− substrate is back side etched to the selected depth using a solution of KOH/water, or alternately TMAH/water. During the wet etch, the N+ membrane area can be electrically biased to provide an etch selectivity in which only the P− substrate is attacked by the wet etchant.
The apparatus is adapted to electrochemically etch the back side of the substrate to form the membrane and open the mask pattern. The apparatus includes an etch chamber adapted to isolate and apply a wet etchant to the back side of the substrate. In addition, the apparatus includes a pressure equalization chamber adapted to apply an inert liquid, such as DI water (de-ionized water), to the front side of the substrate. The pressure equalization chamber equalizes pressure on either side of the substrate, so that a rupture during formation of the membrane is less likely to occur. The apparatus also includes an electrode adapted to apply a voltage potential to the membrane area to insure etch selectivity. Still further, the apparatus includes a surge chamber and a flexible membrane, adapted to transfer pressure pulses generated by the etchant source to the pressure equalization chamber.
The system includes the apparatus and conventional semiconductor fabrication equipment configured to define the membrane area and mask pattern. The semiconductor fabrication equipment can include: an ion implanter for implanting dopants in the substrate to define the membrane area; optical or e-beam pattern generators for defining the mask pattern; a chemical vapor deposition apparatus for growing a TEOS hard mask for the mask pattern; and a reactive ion etcher for etching recesses in the substrate to form the mask pattern.
REFERENCES:
patent: 4966663 (1990-10-01), Mauger
patent: 5110373 (1992-05-01), Mauger
patent: 5401932 (1995-03-01), Hashimoto et al.
patent: 5567551 (1996-10-01), Yahalom et al.
patent: 5672449 (1997-09-01), Loschner et al.
patent: 5968336 (1999-10-01), Rolfson
Behringer, U. and Engelke, H., “Intelligent design splitting in stencil mask technology used for electron- and ion-beam lithography”, J. Vac. Sci. Technol. B 11(6), Nov./Dec. 1993, p. 2400-2403.
Gorgos Kathryn
Gratton Stephen A.
Micro)n Technology, Inc.
Parsons Thomas H
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