Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Reexamination Certificate
1998-02-18
2002-02-19
Ellis, Richard L. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
C712S225000
Reexamination Certificate
active
06349379
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to computer architecture and, in particular, to computer architectures dedicated to the printing or other display of graphical images.
BACKGROUND OF THE INVENTION
An important aspect of the design of any computer architecture is the instruction set, or the way in which instructions are formatted or encoded. Each instruction normally consists of an opcode—that is an instruction as to what is to be done to some data, and one or more operand(s)—that is the data itself or the address at which the relevant data can be located. Generally the operand(s) occupy a fixed length since this provides the advantage that the length of the instruction is fixed with a large resulting simplification of the associated hardware.
In the environment of the present invention it is necessary to perform calculations on large streams of data of variable length. This is different from typical prior art arrangements which typically have fixed quantities of data. Therefore in the present invention there is a requirement that the length of the stream of data be specified in some way.
The present invention is based on the realisation that a convention instruction set requires the processor to (1) fetch the instruction, (2) decode the instruction, (3) fetch the operand, (4) carry out the calculation, and (5) store the result. There is an appreciable amount of time spent on steps (1) and (2) because they are inherently slow and must be performed for each instruction.
However, if these two steps could be combined into a single operation which was performed only once for a relatively long stream of data, then the average of this overhead for each calculation would be substantially reduced since the overhead would be amortized over a large number of calculations. This would reduce the average time for all calculations and result in faster overall operation.
SUMMARY OF THE INVENTION
In accordance with the present invention there is disclosed an image processor for executing a computer instruction set comprising a plurality of instructions each of which has an instruction opcode and at least one operand, wherein said opcode corresponds to a type of calculation to be performed on the operand(s), each operand is data to be processed in said calculation or specifies the address of said data, the result of said calculation represents processed image data, and each instruction includes a length field containing data specifying the number of items of data to be processed or, if said number exceeds the size of said length field, a predetermined location of a previously allocated storage area at which said number is stored, whereby said processor for each instruction processes the corresponding said number of data items to thereby facilitate processing of variable length streams of data.
Preferably the length of all said instructions is both fixed and equal and the time required for the stream data processing exceeds that the time to fetch and decode each of the instructions.
In the following detailed description, the reader's attention is directed, in particular, to
FIGS. 10 and 11
and their associated description without intending to detract from the disclosure of the remainder of the description.
TABLE OF CONTENTS
1.0 Brief Description of the Drawings
2.0 List of Tables
3.0 Description of the Preferred and Other Embodiments
3.1 General Arrangement of Plural Stream Architecture
3.2 Host/Co-processor Queuing
3.3 Register Description of Co-processor
3.4 Format of Plural Streams
3.5 Determine Current Active Stream
3.6 Fetch Instruction of Current Active Stream
3.7 Decode and Execute Instruction
3.8 Update Registers of Instruction Controller
3.9 Semantics of the Register Access Semaphore
3.10 Instruction Controller
3.11 Description of a Modules Local Register File
3.12 Register Read/Write Handling
3.13 Memory Area Read/Write Handling
3.14 CBus Structure
3.15 Co-processor Data Types and Data Manipulation
3.16 Data Normalization Circuit
3.17 Image Processing Operations of Accelerator Card
3.17.1 Compositing
3.17.2 Color Space Conversion Instructions
a. Single Output General Color Space (SOGCS) Conversion Mode
b. Multiple Output General Color Space Mode
3.17.3 JPEG Coding/Decoding
a. Encoding
b. Decoding
3.17.4 Table Indexing
3.17.5 Data Coding Instructions
3.17.6 A Fast DCT Apparatus
3.17.7 Huffman Decoder
3.17.8 Image Transformation Instructions
3.17.9 Convolution Instructions
3.17.10 Matrix Multiplication
3.17.11 Halftoning
3.17.12 Hierarchial Image Format Decompression
3.17.13 Memory Copy Instructions
a. General purpose data movement instructions
b. Local DMA instructions
3.17.14 Flow Control Instructions
3.18 Modules of the Accelerator Card
3.18.1 Pixel Organizer
3.18.2 MUV Buffer
3.18.3 Result Organizer
3.18.4 Operand Organizers B and C
3.18.5 Main Data Path Unit
3.18.6 Data Cache Controller and Cache
a. Normal Cache Mode
b. The Single Output General Color Space Conversion Mode
c. Multiple Output General Color Space Conversion Mode
d. JPEG Encoding Mode
e. Slow JPEG Decoding Mode
f. Matrix Multiplication Mode
g. Disabled Mode
h. Invalidate Mode
3.18.7 Input Interface Switch
3.18.8 Local Memory Controller
3.18.9 Miscellaneous Module
3.18.10 External Interface Controller
3.18.11 Peripheral Interface Controller
1.0. BRIEF DESCRIPTION OF THE DRAWINGS
Notwithstanding any other forms which may fall within the scope of the present invention, preferred forms of the invention will now be described, by way of example only, with reference to the accompanying drawings:
FIG. 1
illustrates the operation of a raster image co-processor within a host computer environment;
FIG. 2
illustrates the raster image co-processor of
FIG. 1
in further detail;
FIG. 3
illustrates the memory map of the raster image co-processor;
FIG. 4
shows the relationship between a CPU, instruction queue, instruction operands and results in shared memory, and a co-processor;
FIG. 5
shows the relationship between an instruction generator, memory manager, queue manager and co-processor;
FIG. 6
shows the operation of the graphics co-processor reading instructions for execution from the pending instruction queue and placing them on the completed instruction queue;
FIG. 7
shows a fixed length circular buffer implementation of the instruction queue, indicating the need to wait when the buffer fills;
FIG. 8
illustrates to instruction execution streams as utilized by the co-processor;
FIG. 9
illustrates an instruction execution flow chart;
FIG. 10
illustrates the standard instruction word format utilized by the co-processor;
FIG. 11
illustrates the instruction word fields of a standard instruction;
FIG. 12
illustrates the data word fields of a standard instruction;
FIG. 13
illustrates schematically the instruction controller of
FIG. 2
;
FIG. 14
illustrates the execution controller of
FIG. 13
in more detail;
FIG. 15
illustrates a state transition diagram of the instruction controller;
FIG. 16
illustrates the instruction decoder of
FIG. 13
;
FIG. 17
illustrates the instruction sequencer of
FIG. 16
in more detail;
FIG. 18
illustrates a transition diagram for the ID sequencer of
FIG. 16
;
FIG. 19
illustrates schematically the prefetch buffer controller of
FIG. 13
in more detail;
FIG. 20
, comprised of
FIGS. 20A and 20B
, illustrates the standard form of register storage and module interaction as utilized in the co-processor;
FIG. 21
illustrates the format of control bus transactions as utilized in the co- processor;
FIG. 22
illustrates the data flow through a portion of the co-processor;
FIG. 23
illustrates an example of data reformatting as utilized in the co-processor;
FIG. 24
illustrates an example of data reformatting as utilized in the co-processor;
FIG. 25
illustrates an example of data reformatting as utilized in the co-processor;
FIG. 26
illustrates an example of data reformatting as utilized in the co-processor;
FIG. 27
illustrates an example of data reformatting as utilized in the co-processor;
FIG. 28
illustrates an example of data reformatting as utilized in the co-p
Amies Christopher
Gibson Ian
Long Timothy Merrick
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