Patent
1997-03-17
1998-07-07
Treat, William M.
395377, G06F 946
Patent
active
057782210
ABSTRACT:
An interrupt system for use with an interruptable data processing system comprising a register for receiving and transmitting storage medium address data and branch and link instruction data, a selector circuit for receiving (i) instructions from a storage medium, (ii) the storage medium address data and (iii) the branch and link instruction data wherein the selector circuit has a first state for outputting data comprising instructions from the storage medium and a second state for outputting data comprising the storage medium address data and the branch and link instruction data. The interrupt system further comprising an instruction processor for processing data outputted by the selector circuit and outputting data for use by the processing system. The instruction processor outputting (i) storage medium address data and (ii) branch and link instruction data for input to the register and (iii) a user status signal when the selector circuit is in the first state and the selector circuit output comprises an asynchronous branch and link instruction. When the selector circuit is in the second state, the instruction processor processes the storage medium address data and the branch and link instruction data and outputs data defining a second program to which the processing system shall branch and the storage medium address at which the processing system shall resume operation according to the first program. The interrupt system further comprising a control circuit for configuring the selector circuit to the second state to transfer the branch and link instruction data to the instruction processor when the control circuit receives the user status signal and an interrupt signal.
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Ahsan Aziz M.
International Business Machines - Corporation
Peterson Peter W.
Treat William M.
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