Boots – shoes – and leggings
Patent
1986-06-02
1988-09-20
Shaw, Gareth D.
Boots, shoes, and leggings
G06F 900
Patent
active
047730412
ABSTRACT:
A referencing unit which creates addresses for main memory. Specifically, this reference unit is pipelined in the manner in which it receives the operators to be executed. Concurrency is achieved by allowing any number of read-type operations to be started before operators that are waiting for a store operation to finish even though these latter operators may appear earlier in the code stream. There are two inputs into the reference unit. Each is provided with a queue, one for receiving operators and address couples and another for receiving the output from the top-of-the-stack mechanism residing in the processor. The former is called an address coupled queue and the latter is called a top-of-stack queue. Since the address couple queue operators require no stack inputs, they enter the reference pipeline, two pipeline levels below where the top-of-stack operators enter the pipeline. This out-of-order execution allows the pipeline to remain full (with address couple queue operators) even though the top-of-stack operator is waiting for an input to become available.
REFERENCES:
patent: 3771138 (1973-11-01), Celtruda et al.
patent: 4390946 (1983-06-01), Lane
patent: 4459666 (1984-07-01), Kruger
patent: 4561052 (1985-12-01), Tateno
patent: 4594655 (1986-06-01), Hao et al.
patent: 4638429 (1987-01-01), Watabe et al.
Burroughs William G.
Hassler Joseph A.
Mills John Gladstone
Peterson Kevin R.
Shaw Gareth D.
Unisys Corporation
Young Mervyn L.
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