Patent
1994-05-17
1997-01-14
Ellis, Richard L.
395726, G06F 930
Patent
active
055948804
ABSTRACT:
A method and apparatus for determining instruction execution ordering in a data processing system (10). In one form, a control bit (52) is used by data processing system (10) to determine whether a standard instruction or a modified instruction is executed. The standard instruction performs a read bus cycle following by a write bus cycle. The bus (12) must be locked between the read and the write cycles in order to maintain coherency in semaphore applications. The modified instruction performs a buffered write bus cycle following by a read bus cycle. The bus (12) does not need to be locked between the write and the read cycles in order to maintain coherency in semaphore applications. Not locking the bus (12) can increase bus bandwidth in some bus systems.
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Gullette James B.
Moyer William C.
Pepe Kara B.
Ellis Richard L.
Hill Susan C.
Motorola Inc.
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