System for error control and phasing in interconnected ARQ-circu

Details System for error control and phasing in interconnected ARQ-circu System for error control and phasing in interconnected ARQ-circu

1976-10-15

1978-05-30

Smith, Jerry

Communications: electrical

Digital comparator systems

178 23A, 178 58A, G08C 2500, H04L 110, G06F 1100

Patent

active

040926303

ABSTRACT:
A system for reducing the time for repeating erroneous signals through a series of interconnected ARQ-circuits (automatic error correction circuits), in which the durations of the repetition cycles of the ARQ-circuits, as compared to one another, are not equal. The system comprises means at a connection point and capable of storing a number of signals related to each propagation time of a circuit located before the connection point, when a circuit located behind the connection point goes through a repetition procedure including means for generating a special signal to indicate when a repetition procedure is in process in one of said ARQ interconnected circuits to prevent the other interconnected ARQ circuits from also going through their repetition procedures.

REFERENCES:
patent: 3641494 (1972-02-01), Perrault et al.
patent: 3879577 (1975-04-01), Progler
patent: 3956589 (1976-05-01), Weathers et al.

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