System for erasing nonvolatile memory

Details System for erasing nonvolatile memory System for erasing nonvolatile memory

2007-06-19

2007-06-19

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185290, C365S185240

Reexamination Certificate

active

10887077

ABSTRACT:
Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls an erase process of performing erasing to the plurality of nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to the nonvolatile memory cell exceeding a pre-write-back level before a depletion level, and a second write process of performing writing to the nonvolatile memory cell exceeding a write-back level after the first write process. Since the occurrence of depletion is suppressed by successively performing the first write process with respect to the nonvolatile memory cells which may exceed the depletion level in the erase process, erasing can be performed to the nonvolatile memory cell without causing depletion halfway therethrough.

REFERENCES:
patent: 5642311 (1997-06-01), Cleveland et al.
patent: 6172909 (2001-01-01), Haddad et al.
patent: 6252803 (2001-06-01), Fastow et al.
patent: 2000-260189 (2000-09-01), None

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