System for distributing clocks using a delay lock loop in a prog

Details System for distributing clocks using a delay lock loop in a prog System for distributing clocks using a delay lock loop in a prog

1995-10-16

1998-04-28

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327147, 327149, 327156, 327 12, 331 11, H03L 708, H03L 7087

Patent

active

057449910

ABSTRACT:
A system (100) for distributing a clock signal to many points on an integrated circuit. The system includes using a delay lock loop with specific digital circuits to accomplish the phase error detection and delay element selection. In one embodiment, two flip-flops are used to detect a phase error. In another embodiment, both macro (202) and micro phase detectors (218) are used and the delay element selection is performed in two stages by using a shift register (210) in a first stage and a counter (220) in a second stage. Another feature of the present invention is, the ability to distribute the reference clock or a synchronized clock to different portions of the circuitry on an integrated circuit. Multiple clock distribution systems are provided which may be selected.

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