System for distributing clocks using a delay lock loop in a prog

Details System for distributing clocks using a delay lock loop in a prog System for distributing clocks using a delay lock loop in a prog

1997-11-17

1999-10-05

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327149, 327 12, 331 11, H03L 708, H03L 7087

Patent

active

059630698

ABSTRACT:
A system (100) for distributing a clock signal to many points on an integrated circuit. The system includes using a delay lock loop with specific digital circuits to accomplish the phase error detection and delay element selection. In one embodiment, two flip-flops are used to detect a phase error. In another embodiment, both macro (202) and micro phase detectors (218) are used and the delay element selection is performed in two stages by using a shift register (210) in a first stage and a counter (220) in a second stage. Another feature of the present invention is, the ability to distribute the reference clock or a synchronized clock to different portions of the circuitry on an integrated circuit. Multiple clock distribution systems are provided which may be selected.

REFERENCES:
patent: Re357979 (1998-05-01), Graham et al.
patent: 4494021 (1985-01-01), Bell et al.
patent: 4604582 (1986-08-01), Strenkowski et al.
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4617479 (1986-10-01), Hartmann et al.
patent: 4633488 (1986-12-01), Shaw
patent: 4637018 (1987-01-01), Flora et al.
patent: 4677318 (1987-06-01), Veenstra et al.
patent: 4689581 (1987-08-01), Talbot
patent: 4713792 (1987-12-01), Hartmann et al.
patent: 4719593 (1988-01-01), Threewitt et al.
patent: 4868522 (1989-09-01), Popat et al.
patent: 4871930 (1989-10-01), Wong et al.
patent: 4899067 (1990-02-01), So et al.
patent: 4912342 (1990-03-01), Wong et al.
patent: 4959646 (1990-09-01), Podkowa et al.
patent: 5072195 (1991-12-01), Graham et al.
patent: 5075575 (1991-12-01), Shizukuishi et al.
patent: 5079519 (1992-01-01), Ashby et al.
patent: 5118975 (1992-06-01), Hillis et al.
patent: 5121006 (1992-06-01), Pedersen et al.
patent: 5133064 (1992-07-01), Hotta et al.
patent: 5173617 (1992-12-01), Alsup et al.
patent: 5204555 (1993-04-01), Graham et al.
patent: 5218314 (1993-06-01), Efendovich et al.
patent: 5223755 (1993-06-01), Richley
patent: 5241224 (1993-08-01), Pedersen et al.
patent: 5260608 (1993-11-01), Marbot
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5298866 (1994-03-01), Kaplinsky
patent: 5349544 (1994-09-01), Wright et al.
patent: 5350954 (1994-09-01), Patel et al.
patent: 5355037 (1994-10-01), Andresen et al.
patent: 5397943 (1995-03-01), West et al.
patent: 5418499 (1995-05-01), Nakao
patent: 5420544 (1995-05-01), Ishibashi
patent: 5506878 (1996-04-01), Chiang
patent: 5537069 (1996-07-01), Volk
patent: 5544203 (1996-08-01), Casasanta et al.
patent: 5646564 (1997-07-01), Erickson et al.
patent: 5742180 (1998-04-01), DeHon et al.
patent: 5744991 (1998-04-01), Jefferson et al.
patent: 5777360 (1998-07-01), Rostoker et al.
patent: 5815016 (1998-09-01), Erickson
patent: B14617479 (1993-09-01), Hartmann et al.
Dr. Dao-Long Chen, "Designing On-Chip Clock Generators," in Circuits and Devices, Jul. 1992, pp. 32-36.
Mark G. Johnson et al., "A Variable Delay Line PLL for CPU-Coprocessor Synchronization," in IEEE Journal of Solid State Circuits, vol. 23, No. 5, pp. 1218-1223.
Ian A. Young et al., "A PLL Clock Generator With 5 to 110 MHz of Lock Range for Microprocessors," IEEE Journal of Solid State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1599-1607.
Uming Ko et al., "A 30-ps Jitter, 3.6-us Locking 3.3-Volt Digital PLL for CMOS Gate Arrays," IEEE 1993 Custom Integrated Circuits Conference, pp. 23.3.1-23.3.4.
Florence Lee, "PLL Application Note," LSI Logic Corporation, Nov. 8, 1991, pp. 1-28.
Advanced Micro Devices,"Am2971 Programmable Event Generator (PEG)," Jul. 1996, pp. 4-286 to 4-309.
Advanced Micro Devices, "AmPAL 23S8," Oct. 1996, pp. 4-102 to 4-121.
Monolithic Memories, "Programmable Array Logic PAL20RA 10-20," Jan. 1988, pp. 5-95 to 5-102.
Zaks, et al, "From Chips to Systems: An Intro. to Microcomputers," Sybex, 1987, pp. 54-61.

Affiliated with

Also associated with

Rating

System for distributing clocks using a delay lock loop in a prog does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System for distributing clocks using a delay lock loop in a prog, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System for distributing clocks using a delay lock loop in a prog will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1175854