Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
1998-01-26
2001-04-03
Kim, Jung Ho (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S565000, C333S012000
Reexamination Certificate
active
06211714
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a system for providing a high speed serial communications link allowing fully duplexed serial data communication. In particular, this invention relates to an interface circuit for interconnecting devices with parallel datapaths via such a serial link.
As electronic and computer technology continues to evolve, communication of information among different devices, either situated near by or at a distance becomes increasingly important. For example, it is now more desirable than ever to provide for high speed communications among different chips on a circuit board, different circuit boards in a system, and different systems with each other. It is also increasingly desirable to provide such communications at very high speeds, especially in view of the large amount of data required for data communications in intensive data consuming systems using graphical or video information, multiple input-output channels, local area networks, and the like.
It is particularly desirable to enable individual personal computers, workstations, or other computing devices, within which data is normally internally transferred using parallel data buses, to communicate with each other over relatively simple transmission lines. Such transmission lines typically include only one or two conductors, in contrast with the 64-bit and wider data paths within computing systems now commonly available.
There have been a number of commercially available products which attempt to provide high speed conversion of parallel data to serial form and transmission over a serial link. The Hewlett-Packard G-link chip set is one such product. That chip set includes a transmitter set and is capable of handling 20- or 24-bit wide parallel data. To obtain the necessary speed, however, the chip set is fabricated using a bipolar process, and the receiver and transmitter require separate chips. Such a solution is highly power consumptive and expensive. It also employs a conventional approach to parallel-to-serial data conversion, that is, the use of a phase-locked loop oscillator operating at the transmission rate. Such devices typically introduce noise into the silicon substrate and interfere with other phase-locked loop circuitry on the chip. This makes it difficult to integrate many channels on a single chip.
Another commercial solution has been provided by Bull of France. The Bull technology employs a frequency multiplier for parallel to serial data conversion. Such devices typically introduce noise into the silicon substrate and interfere with other multipliers on the chip. In addition, the Bull technology uses an exclusive OR tree for parallel to serial conversion. The use of exclusive OR trees is well known, together with the difficulty of equalizing the delay through all paths of such devices. The Bull technology employs a delay-locked loop circuit that mandates the use of a special coding scheme which could result in reduced coding efficiency.
SUMMARY OF THE INVENTION
This invention provides a very high speed data serializer capable of converting parallel data to serial data at speeds greater than one gigabit per second, and a data/clock recovery circuit that does not require an individual independent clock for each channel. Despite enabling data conversion at extremely high rates, the invention can be fabricated relatively inexpensively using well known complementary MOS technology, as opposed to gallium arsenide, bipolar, and other technologies conventionally employed to fabricate such high speed devices. Also, the invention provides a technique for converting serial data to parallel data in which only a single oscillator is required for many channels, thereby eliminating the possibility of injection effects which make all the oscillators attached to individual channels falsely synchronize to a single frequency in prior art devices. In addition, the technique employed avoids the use of exclusive OR trees, and their accompanying difficulty of equalizing delay paths. In the preferred embodiment, the parallel-to-serial conversion is achieved using one or more latches to latch data in the parallel data stream before conversion. The output terminal of each latch is connected to a corresponding AND gate. Other terminals of each AND gate are connected to receive phased clock signals. When the clock signals are enabled, the latched data is supplied at the output terminal of the AND gate, Which is in turn coupled to an input terminal of multiple input terminal OR gate. As the clock signals are phased, data from each sequential AND gate is supplied to the OR gate, and then serially from the OR gate to a suitable transmitter or other apparatus.
In one embodiment, a circuit for converting N bits of parallel data into a serial data string includes a register having at least N storage locations for temporarily storing the parallel data. A source of an appropriate number of clock signals, with each clock signal having a different phase than every other clock signal is provided, and a different clock signal is connected to each one of a series of AND gates. Each of the AND gates is also connected to receive an appropriate one of the bits of parallel data. An OR gate with the corresponding number of input nodes is then coupled to the output of each AND gate. By appropriate phasing of the clock signals. the data presented at the input terminals of the AND gates is converted to serial form by the OR gate and supplied to a transmitter or other apparatus.
In a further embodiment, the present invention is a system for distributing clock signals with minimum skew. A plurality of clock signals, each having a different phase, are conducted using a plurality of conductors. The conductors are substantially parallel and positioned adjacent to one another. Each conductor carries a different phase from adjacent conductors. This minimizes and nullifies the adverse effect of capacitive coupling between the adjoining clock conductors. In an embodiment, the clock signals are distributed such that during a signal transition on one conductor, the signals on adjacent conductors are substantially static.
Furthermore, additional dummy conductors may be placed at the edges of the plurality of parallel conductors to provide symmetrical capacitive coupling for the edge conductors. The capacitive coupling for edge conductors will be substantially similar (and symmetrical) to the coupling seen on the interior conductors. The dummy conductors may carry a duplicate clock signal to one of those carried by an interior conductor.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.
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Kim Jung Ho
Sun Microsystems Inc.
Townsend and Townsend / and Crew LLP
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