System for displaying graphics in a digital television receiver

Details System for displaying graphics in a digital television receiver System for displaying graphics in a digital television receiver

2006-06-27

2006-06-27

Hsia, Sherrie (Department: 2614)

Television

Image signal processing circuitry specific to television

Special effects

C348S564000, C348S600000

Reexamination Certificate

active

07068324

ABSTRACT:
A circuit for displaying graphics in a digital television receiver includes an MPEG decoder which has as input a video data stream in digital format, a central memory for storing decoded video data and graphics data, a video output unit and a graphics output unit to which video data and graphics data, respectively, are fed from the central memory, a mixer to which an output signal from the video output unit is fed, and a switch through which the output signal of the graphics output unit is selectively fed to the mixer. Horizontal and vertical synchronization signals from the MPEG decoder may be fed to the video output unit, while horizontal and vertical synchronization signals from various sources (including those from the MPEG decoder) may be selectively fed through a multiplexer to the graphics output unit. One buffer memory each may be placed before the video output unit and the graphics output unit, respectively, each memory unit buffering the corresponding data retrieved from the central memory. A signal generator may be provided which generates horizontal and vertical synchronization signals and provides these to the multiplexer. Additional horizontal and vertical synchronization signals may be fed to the multiplexer from an external connector. The video output unit may be operated at a first clock frequency, while the graphics output unit may be operated at a second clock frequency. This helps to achieve essentially independent processing of the graphics data and the video data. When the switch is closed, the first and second clock frequencies may be the same, and the same horizontal and vertical synchronization signals may then be sent to both the video output unit and the graphics output unit.

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R. Geppert et al. “A Digital Video Encoder for DBS Systems,” Proceedings of the International Conference on Consumer Electronics, IEEE, vol. Conf. 12, p. 254-255.

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