Computer graphics processing and selective visual display system – Display driving control circuitry – Intensity or color driving control
Reexamination Certificate
2002-04-18
2003-07-22
Garber, Wendy R. (Department: 2612)
Computer graphics processing and selective visual display system
Display driving control circuitry
Intensity or color driving control
C345S090000, C348S671000, C348S383000, C341S143000
Reexamination Certificate
active
06597371
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a method and apparatus particularly suited for driving a row-column addressable pixel matrix display including, for example, analog type displays such as liquid crystal (LCD) and field emission (FED) and digital type displays such as ferro electric liquid crystal (FLD) and digital micromirror (DMD).
BACKGROUND OF THE INVENTION
Many video display devices can be considered as comprising a matrix of latent pixels each of which can be selectively illuminated to collectively form a frame image. A typical laptop computer display physically defines on the order of 25-80 pixels per inch. A frame image might typically be formed by approximately one million pixels, i.e., 1024 pixels wide×768 pixels high. Depending upon the physical persistence characteristics of each display device and the rate at which image information changes, it is generally necessary to refresh frame images at a rate of at least 60 frames per second (fps) to avoid apparent flicker. This technique of frame flashing has been and remains the dominant method of electronically displaying images for various video display applications, regardless of whether the image information is presented in digital or analog form. In either case, the video output circuitry generally produces an analog output to drive the display device, e.g., in RGB or NSTC format.
Applicant's prior U.S. Pat. Nos. 5,248,971; 5,515,046; and 5,569,315 describe a focal plane imager (or camera) which utilizes a multiplexed oversampling analog to digital modulation technique to produce an output bit stream for displaying the focal plane image on a monitor. The disclosures in these patents are, by reference, incorporated herein.
SUMMARY OF THE INVENTION
The present invention is directed to an enhanced method and apparatus for driving a pixel addressable video display which avoids frame flashing and instead modulates each display pixel, e.g., on or off, during successive short time increments. The psycho-physical response characteristic of the human eye acts as a low pass filter enabling a human observer to extract a real time flicker free apparent gray or color scale image.
Apparatus in accordance with the invention functions to drive a pixel addressable video display (preferably a row-column, i.e., X·Y display) in response to a digital image file containing X·Y N-bit pixel values. The file can be configured in any of various formats, e.g., TIF, JPG, AVI BMP, etc. In accordance with the invention, each N-bit pixel value (i.e., input word) refreshed at a frequency F1 is converted to an M-bit output pixel value at a frequency F2 where N>M and F2>F1. In a preferred exemplary embodiment, an eight (i.e., N) bit input pixel value refreshed at 60 (i.e., F1) times per second is converted to a one (i.e., M) bit output pixel value streaming at 420 (i.e., F2) bits per second. The output pixel value stream directly modulates a video display pixel. Where M=1, the display pixel is modulated between two possible states, e.g., on-off. In other embodiments, e.g., where M=3, each display pixel is modulated to define one of eight possible states.
Embodiments of the invention are particularly suited for use with video displays comprised of at least 10000 addressable pixels, e.g., X≧100, Y≧100.
Preferred embodiments of the invention utilize an oversampling data modulator to convert the sequence of N-bit words refreshed at F1 to an M-bit stream at a greater frequency. Oversampling data converters, particularly those implemented as Delta-Sigma (sometimes referred to as Sigma-Delta) loops, are widely discussed in the literature; e.g., see (1)
Oversampling Delta
-
Sigma Data Converters
, edited by J. C. Candy and S. C. Temes, IEEE Press and
Delta
-
Sigma Data Converters
, edited by S. R. Norsworthy, R. Schreiver, and S. C. Temes, IEEE Press.
The use of oversampling for digital to analog conversion for a small number of analog channels is well known. For example, in applications such as CD players, digitally coded values are sampled and regenerated at a higher rate. The high rate multibit data is then sampled by an oversampling modulator where the data is reduced in the number of bits, typically to one-bit, and the data sample rate is increased. A precise voltage is then generated from the one-bit high sample rate data with a low resolution DAC. To recover a precision analog signal, the DAC output is filtered by a low pass filter, eliminating the high frequency component, and passing the residual low frequency analog data. The use of delta-sigma converters for more than a few, e.g., up to one hundred, analog outputs is generally prohibitive since each analog output requires its own continuous filter of the data.
In a preferred embodiment of the present invention, an oversampling data modulator provides a one-bit data stream for each display pixel. Each data stream, which essentially has the form of a pulse density modulated signal, directly drives a single display pixel to pulse it either on or off to produce a real time apparent gray or color scale pixel image to the eye of an observer. The psycho-physical response of the human eye acts as a low pass filter allowing it to extract a flicker free image from the entire matrix of display pixels.
In an alternative embodiment of the invention, an oversampling data modulator is used to provide a multibit data stream (e.g. M=3) for each display pixel. Each data stream drives a single display pixel to cause it to define a particular one of 2
M
states.
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McIlrath, L.; “A Low Power, Low Noise, Ultra-Wide Dynamic Range CMOS Imager with Pixel-Parallel A/D Conversion”; 2000, IEEE Symposium on VLSI Circuits Digest of Technical Papers.*
Haurie et al.; “A Multiplier-Free Structure for 1-Bit High-Order Digital Delta-Sigma Modulators”; Aug. 1995; Proceedings of the 38th annual Symposium; vol. 2 13-16, pp. 889-892.
Freilich Hornbaker & Rosen
Garber Wendy R.
Villecco John M.
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