System for digital filtering in a fixed number of clock cycles

Details System for digital filtering in a fixed number of clock cycles System for digital filtering in a fixed number of clock cycles

1998-02-10

2001-01-16

Malzahn, David H. (Department: 2787)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S313000, C708S523000

Reexamination Certificate

active

06175849

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to digital processing and testing techniques, and more particularly to digital processing relating to digital filtering techniques.
2. Background of Related Art
Efficient and inexpensive digitization of telephone grade audio has been accomplished for many years by an integrated device known as a “codec.” A codec (short for COder-DECoder) is an integrated circuit or other electronic device which combines the circuits needed to convert analog signals to and from digital signals, e.g., Pulse Code Modulation (PCM) digital signals.
Early codecs converted analog signals at an 8 KHz rate into 8-bit PCM for use in telephony. More recently, the efficiency and low cost advantages of codecs have been expanded to convert analog signals at a 48 KHz sampling rate into 16-bit stereo (and even up to 20-bit stereo) for higher quality use beyond that required for telephony. With higher quality audio capability, today's codecs find practical application in consumer stereo equipment including CD players, modems, computers and digital speakers.
With the development of codecs for these more sophisticated purposes came the need to improve the analog signal-to-noise (S/N) ratio to at least 75 to 90 dB. Improved S/N ratios have been achieved largely by separating the conventional codec into two individual sub-systems and/or two separate integrated circuits (ICs): a controller sub-system handling primarily the digital interface to a host processor, and an analog sub-system handling primarily the interface to, mixing and conversion of analog signals. This split digital/analog architecture has been documented most recently as the “Audio Codec '97 Component Specification”, Revision 1.03, Sep. 15, 1996, as revised in “Audio Codec '97”, Revision 2.0, Sep. 29, 1997 (collectively referred to herein as “the AC '97 specification”). The AC '97 specification in its entirety is expressly incorporated herein by reference.
FIG. 1
is a generalized block diagram of a conventional split-architecture audio codec conforming to the AC '97 specification. Audio codecs conforming to the AC '97 specification accommodate audio sources from CD players, auxiliary devices such as stereo equipment, microphones and/or telephones.
As shown in
FIG. 1
, currently known split-architecture audio codecs contemplate a host processor, an audio codec (AC) controller sub-system or IC
402
, and an AC analog sub-system or IC
404
. The connection between the AC controller sub-system
402
and the AC analog sub-system
404
is currently defined as a five-wire time division multiplexed (TDM) interface controlled by an AC-link
406
. The AC controller sub-system
402
may be a stand alone device, or it may be a portion of a larger device such as a Peripheral Component Interconnect (PCI) interface device. PCI is a processor-independent, self-configuring local bus. Alternatively, the AC controller sub-system
402
may be a part of a central processing unit (CPU).
Because of the capabilities of the split digital/analog architecture (i.e., AC controller sub-system
402
and AC analog sub-system
404
), the AC '97 specification includes a significant amount of flexibility intended to capture a large market by satisfying many consumer-related audio needs. For instance, the conventional AC analog sub-system
404
includes interface capability to accept input from multiple sources and to mix the analog signals from those multiple sources. Possible analog signal sources include a CD, video, or telephone line.
FIG. 2A
is a diagram showing relevant features of the conventional AC analog sub-system
404
. The relevant features include an analog mixing and gain control section
200
accepting input from various analog audio sources
210
including a PC Beep signal, a telephone input, two microphone inputs, a general line in, a signal from a CD player, an analog signal from a video source, and an auxiliary input. The analog mixing and gain control section
200
mixes analog signals input from the various analog audio sources
210
, and outputs up to three separate analog channels for digitization in analog-to-digital (A/D) converters
206
a,
206
b,
206
c.
A digital interface
202
prepares the mixed, digitized audio signals output from the A/D converters
206
a
-
206
c
into a serial data stream for transmission via an AC link
406
.
In the opposite direction, digital audio signals received from the serial data stream of the AC link
406
by the digital interface
202
are converted back into analog audio signals by digital-to-analog (D/A) converters
204
a,
204
b,
and output to the analog mixing and gain control section
200
for gain control and output on the various desired analog audio source lines
210
.
FIG. 2B
is a more detailed schematic diagram of the analog mixing and gain control section
200
of the AC analog subsystem
404
shown in FIG.
2
A. In
FIG. 2B
, the analog signals from the analog audio sources
210
are gain adjusted in analog form by analog gain adjusters
300
, then mixed in analog mixer
310
. A secondary analog mixer
312
allows the inclusion of the PC beep signal and telephone signal into the mixed analog product. The mixed analog signal is gain adjustable in gain adjuster
302
and output from the Analog mixing and gain control module
200
and AC analog subsystem
404
. Analog mixer
314
mixes the left and right channels of the summed analog signal to provide a mono signal output, which is gain adjusted in analog gain adjuster
304
. Analog mixer
316
similarly provides a mono output from the stereo output signal.
For recording, a multiplexer (MUX)
320
multiplexes signals from the various sources and allows selection of one per channel of the various sources together with a microphone signal for output to a master analog gain adjuster
306
. The three gain adjusted analog signals output from MUX
320
are finally converted into digital signals by A/D converters
206
a,
206
b
and
206
c.
Thus, the mixing and gain control of a conventional AC analog subsystem
404
is typically handled with analog circuitry.
While it is suitable to mix and gain adjust audio signals in analog form for certain applications as shown in
FIGS. 2A and 2B
, analog features on an integrated circuit require significant amounts of space in the AC analog subsystem
404
. Analog circuitry also generally provides a larger source of electrical noise causing cross-talk or other disadvantageous side effects. Thus, to improve a signal to noise ratio of output signals, it is desirable to provide digital testing and processing techniques, e.g., to minimize the analog circuitry in the AC analog subsystem.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, a digital filter comprises a multiplier and an adder. A first plurality of latches present latched data samples to the multiplier in each of four multiplier clock cycles; and a second plurality of latches present latched data samples to the adder in each of four adder clock cycles. At least one of the four multiplier clock cycles overlap in time with the four adder clock cycles.
A method of providing a plurality of digital filter channels in a fixed number of clock cycles in accordance with the present invention comprises the performance of three multiplication calculations relating to a first one of the plurality of digital filter channels, in three multiplication clock cycles, respectively. Four addition calculations are performed relating to a first one of said plurality of digital filter channels, in four addition clock cycles, respectively. A result of one of the addition calculations is multiplied by a scaling factor in a fourth multiplication clock cycle to arrive at an output for the first one of the plurality of digital filter channels. At least one of a multiplication calculation and an addition calculation are performed for a second one of the plurality of digital filters simultaneously with at least one of the previous steps of the meth

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