System for detecting and isolating static bit faults in a networ

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G06F 1100

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active

041819691

ABSTRACT:
A digital processor comprising a network of arithmetic units and including apparatus for detecting and isolating a static bit fault therein is disclosed. A plurality of first arithmetic units of the network employ non-linear type operations. Each of the first arithmetic units arithmetically operate on a corresponding number of the binary coded digital input words of the network to produce a first output binary coded digital word which is coupled to the remaining network of arithmetic units. Corresponding to each of the first arithmetic units, there is provided a modulo 3 model to emulate in modulo 3 arithmetic the operation thereof and to compare the result of the modulo 3 emulation with the modulo 3 equivalent of a preselected word from the corresponding first arithmetic unit, the preselected word being intermediate the non-linear operation performed thereby. A non-equivalence condition resulting from the comparison is indicative of a static bit fault. Another modulo 3 model is provided to emulate in modulo 3 arithmetic the remaining network of arithmetic units by processing the second output words and the modulo 3 equivalent of the corresponding at least one input word. The another modulo 3 model compares the result of its emulation to the modulo 3 equivalent of the corresponding at least one output word for a non-equivalence condition which is also indicative of a static fault. The comparisons are monitored for non-equivalence conditions to detect a static bit fault and isolate the source of the detected static bit fault.

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