System for decoding self-clocking data signals

Details System for decoding self-clocking data signals System for decoding self-clocking data signals

1987-10-07

1988-11-29

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

328151, 375110, H04L 2714

Patent

active

047886951

ABSTRACT:
A coherent detection and decoding circuit coherently recovers data embedded in a self-clocking data signal by recovering the clock in one integrate and dump circuit and recovering the data in a second integrate and dump circuit. The two integrate and dump circuits are connected to the source of self-clocking data signal and to one of the outputs from a clock phase select switch which produces an inphase clock signal and a NOT inphase clock signal. The inphase clock signal is connected to the integrate and dump circuit which produces the output data signal and the NOT inphase clock signal is connected to the clock recovery integrate and dump circuit. When the presence of a data pulse is detected in the clock phase detection circuit the output signal is coupled to the clock phase select switch so as to reverse the output clock signals and synchronize the inphase clock signal with the data embedded in the self-clocking data input signal.

REFERENCES:
patent: 3626298 (1971-12-01), Paine
patent: 3789303 (1974-01-01), Hoffman et al.
patent: 4088832 (1978-05-01), Eastmond
patent: 4520321 (1985-05-01), Nakatsugawa

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