Coded data generation or conversion – Digital code to digital code converters – To or from run length limited codes
Reexamination Certificate
1999-07-16
2001-07-10
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from run length limited codes
C360S040000, C714S701000
Reexamination Certificate
active
06259385
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to a system of coding within a data transceiving system and, more particularly, to use of run-length constrained convolutional codes, enhancing system efficiency and reducing data error rates.
BACKGROUND OF THE INVENTION
Circuitry and systems for encoding and decoding data are used extensively in modern electronics, especially in applications involving the communication or storage of data. Coding is implemented, and coding techniques are employed, by system designers seeking to provide various system functionalities.
One such functionality is detection and correction of errors in the data being processed by the system. Coding is employed to organize the data into recognizable patterns for transmission and receipt. This is accomplished by the introduction of redundancy into the data being processed by the system. Such functionality reduces the number of data errors, resulting in improved system reliability.
Another prevalent functionality addressed with coding techniques is system timing maintenance and clock recovery. Coding systems are often employed in conjunction with the data transmitted; exploiting redundancy introduced into the data to maintain or stabilize system timing, and to enable clock recovery.
Conventional methods of coding provide separate functional elements to independently address the timing and error reduction demands of the system.
As performance and efficiency demands of data transceiving systems are increased, coding systems and structures can be optimized to provide enhanced system efficiency while reducing system overhead. Appropriate design of a coding system can efficiently address system timing requirements and contribute to reduction of system error rates.
SUMMARY OF THE INVENTION
Data processing is used extensively in modem electronics; whether the data is being stored and retrieved, as in a computer, or the data is being transmitted and received, as in a telecommunications system. Transceiving and processing large amounts of data at demanding system speeds gives rise to a number of challenges for system designers. A significant one of such challenges is the problem of addressing errors introduced into the data by processing. Depending on the nature of the data processing system, there are many possible sources of data errors. Examples of such sources include inter-symbol interference, in a data storage context, and noise and signal attenuation in a data transmission context.
A common measure of the magnitude or frequency of errors occurring in the data is referred to as the bit error rate (“BER”). The bit error rate can be defined generally as a relation between the number of data bits in error and the total number of data bits processed.
In the past, designers could decrease BER by increasing the signal power associated with the data being transmitted. By increasing signal power, effects of noise and interference were diminished, allowing for fewer errors. This approach is not desirable in many of today's electronic systems, however, as many of these systems demand minimal power consumption throughout the system. Additionally, where inter-symbol interference is a factor, the power of interfering signals increase proportionally, rendering this approach useless.
Another approach to decreasing BER has employed various coding techniques, formatting the data for processing. These coding techniques commonly introduce redundancy into the data about to be processed, such that the data is organized into predetermined patterns. This reduces the BER. Another system using no coding and having the same BET would require higher signal power to be transmitted. The reduction in the transmitted power achieved by the former system is referred to as coding gain.
Coding techniques have also been utilized to allow system designers to provide other functionality within the system. Specifically, redundancy of the data being processed by a system has been exploited to maintain a system timing sequence desired by the user.
Conventional methods of addressing these timing issues employ run length limited (“RLL”) encoding and decoding structures. RLL structures are generally employed to constrain the the number of zero bits (“zeroes”) transmitted consecutively by a processing system. The RLL structures enforce minimum and maximum thresholds, and are typically designated by RLL(min, max). Thus, in an RLL(0,8) system, for example, the minimum number of consecutive zeroes allowed is 0 (no minimum requirement), and the maximum number of consecutive zeroes allowed is 8. Too many zeroes transmitted in the data being processed may cause system timing circuitry to run out of synchronization; too few may cause inter-symbol interference. Either case may result in numerous errors in the data transceiving. Thus, the sole purpose for RLL coding structures is the maintenance of timing synchronization in the system; no other functionality is associated with the RLL structures.
However, in a data processing system employing an RLL structure, the probability of an RLL constraint being violated is very small; being roughly equivalent to 2 raised to the power of the negative of the threshold value. For example, in an RLL (0,8) system, the probability of 8 consecutive zeroes being transmitted in the data processed would be roughly equivalent to 2
−8
. Thus, occurrence of such constraint violations is very infrequent, rendering the RLL structure superflous during most of the system operation. RLL structures thus represent unused system overhead (i.e. underutilized circuitry or other implementation structure) during most of the system operation.
It is thereby desirable to provide a coding system that ensures system timing and synchronization without requiring unutilized or underutilized system overhead.
Further, conventional methods employ separate coding systems, distinct and independent from the RLL structures, to address error reduction concerns and effect coding gain. Standard error detection/correction codes are normally used for obtaining coding gain. Standard codes introduce redundancy into data being processed by the system. This patterning of data utilizes more processed data bits to represent a lesser number of actual information data bits. Redundancy is introduced by the system in a pattern predetermined by the system designer or user. Such patterning allows a system designer or user to designate particular sequences of data as allowable, or dis-allowable, by the system.
As data is processed by the system, noise, interference, and other factors may alter the data. Using these standard codes to disallow certain sequences of data, a system can evaluate the data processed. If the data possibly or actually contains errors, the system can then map it to the closest allowable data sequence designated by the code. This methodology is often referred to as maximum likelihood detection.
Convolutional codes have been employed as sources of coding gain. However, conventional convolutional codes require a significant number of data bits to be addressed by the system. In many applications, such as high performance data storage systems—where density and reliability demands are constantly increasing—results yielded by normal convolutional codes are not desirable, as they require too many data bits.
It is thereby desirable to provide a coding system that is efficiently optimized to provide coding gain in system operation.
Apparently, a heretofore unrecognized problem in systems employing RLL coding structures to timing constraints has been the system efficiency resulting from unutilized or underutilized system overhead associated with dedicated RLL structures, actual activation of which is rare.
It is thereby further desirable to provide an optimized code structure that dually ensures system timing and synchronization and efficiently provides coding gain in system operation.
The present invention overcomes the aforementioned limitations of current methods by a system that provides coding structure adapted to address b
Feygin Gennady
Muhammad Khurram
Brady W. James
Chang Daniel D.
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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