System for data synchronization between two devices using four t

Details System for data synchronization between two devices using four t System for data synchronization between two devices using four t

1995-11-03

1998-07-14

Butler, Dennis M.

395558, 395559, G06F 104

Patent

active

057817650

ABSTRACT:
A system for data synchronization in a bus interface unit (12) controls the flow of data between data processor (10) operating at a higher clock rate and the address and data buses operating at a lower clock rate. The data synchronization system incorporates circuit paths operating in four different clock domains: core-rate, bus-rate, transfer-rate, and receive-rate. Circuits processing data solely at the higher clock rate of the data processor or the lower clock rate of the address and data buses operate in the core-rate or bus-rate domains, respectively. The transfer-rate domain is used to transfer data from the core-rate to the bus-rate. Conversely, the receive-rate domain is used to transfer data from the bus-rate to the core-rate. The data synchronization system provides a general solution to the problem unreliable half cycle data paths.

REFERENCES:
patent: 4893271 (1990-01-01), Davis et al.
patent: 5162667 (1992-11-01), Yasui et al.
patent: 5448715 (1995-09-01), Lelm et al.
patent: 5471587 (1995-11-01), Fernando
patent: 5600824 (1997-02-01), Williams et al.

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