Abrading – Machine
Reexamination Certificate
1999-04-26
2002-03-12
Eley, Timothy V. (Department: 3723)
Abrading
Machine
C451S036000, C451S446000, C451S559000, C210S539000, C137S587000
Reexamination Certificate
active
06354921
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor manufacture and, more particularly, to an improved method for Chemical Mechanical Polishing (CMP) in the manufacture of silicon wafers.
Interconnect structures of integrated circuits (ICs) generally take the form of patterned metallization lines that are used to electrically interconnect devices and to provide interconnection with external circuitry. By way of example, IC devices may include complementary metal oxide semiconductor (“CMOS”) devices having diffused source and drain regions that are separated by channel regions, and gates that are located over the channel regions. In practice, an IC chip may include thousands or millions of devices, such as CMOS transistors.
Conventionally, a dielectric layer (e.g., silicon dioxide) is deposited over the devices that are formed on a substrate, and via holes are formed through the dielectric layer to the devices below. As is well known in the art, photolithography “patterning” is typically accomplished by depositing a photoresist layer over the dielectric layer, selectively exposing the photoresist to light through a patterned reticle having via hole patterns, developing the photoresist to form a photoresist via mask, and etching the exposed dielectric layer to form the via holes that lead to a lower level. Once the via holes are formed, a conductive material such as tungsten (W) is used to fill the via holes to define what are known as “tungsten plugs.” Once the tungsten plugs are formed, a metallization layer is formed over the dielectric layer and the tungsten plugs. The metallization layer is then patterned using conventional photolithography and plasma etching techniques to define a first level of interconnect metal routing. This process may then be repeated if additional layers of interconnect structures are desired.
To facilitate discussion, a semiconductor substrate will typically have a number of layers fabricated thereon. In this example, the semiconductor substrate has a first dielectric layer deposed over its surface, and a first metallization layer patterned over the first dielectric layer. A second dielectric layer is then deposited over the first dielectric layer and the first metallization layer. Before a second metallization layer is patterned over the second dielectric layer, via holes are etched and filled with a tungsten material to form tungsten plugs. At this point, the second metallization layer is plasma etched to define the desired interconnect lines.
The dielectric layer used to isolate the metal lines forms a conformal coating taking on the surface features of the metal lines. This surface is not planar due to the spaces between the metal lines and causes problems with the focusing of the photolithography process. As the number of levels of interconnects increases, the focusing problem increases. Some methods of selective deposition of dielectric and selective etching have been used to improve the surface feature of the wafer, however, this is a costly and slow process. Also, there are problems with controlling the dielectric thickness and coverage of the metal lines to provide adequate insulation from noise and shorting between levels.
It is obvious that the more planar the surface of the wafer, the smaller the line spacing of the device. A planar surface provides a uniform layer of photoresist on the wafer so the exposure of the photoresist is more constant and controlled. This reduces the variability in the line width and spacing and therefore a more reliable device. The method of planarization of the surface of the wafer must be repeatable, accurate, and not cost prohibitive. It must also provide for the volume of wafers processed and the number of levels that will require planarization.
Because CMOS semiconductor circuits are continuing to decrease in size, and more devices are packed into smaller IC chips, more densely integrated interconnect structures will be required. However, this dense integration has the effect of pushing the limits of conventional photolithography patterning, which necessarily makes photolithography mask misalignments more likely to occur. Of course, when more misalignments occur, more paths will result, thereby increasing the number of exposed tungsten plugs.
Chemical Mechanical Polishing (CMP) is widely used for manufacturing semiconductors. CMP is very effective for planarizing geometries that are not widely isolated. CMP processes planarize the surface of semiconductor wafers to a desired thickness. In a typical CMP process, a wafer attached to a carrier is pressed against a polishing pad in the presence of a slurry. The slurry contains abrasive particles that mechanically remove material from the wafer and chemicals that chemically treat the material that is ultimately polished. Waste material eventually accumulates on the planarizing surface of the polishing pad during planarization which diminishes the pads effectiveness. The waste matter on the pad reduces the effectiveness and the uniformity of the planarizing surface of the polishing pad. The waste matter accordingly reduces throughput of the CMP process and the uniformity of the polished surface on the wafer. Accordingly, it is necessary to periodically clean the planarizing surface of a polishing pad. Planarizing surfaces of polishing pads are conventionally cleaned by brushing the pad with a stiff brush, but U.S. Pat. No. 5,616,069 teaches a method of using a pad scrubber to clean the planarizing surface of a polishing pad used in CMP processing of semiconductor wafers. The pad scrubber has a fluid manifold and a plurality of nozzles coupled to the manifold to clean the pad as it is used in the CMP process. U.S. Pat. No. 5,816,891 discloses a method and apparatus for performing chemical mechanical polishing of oxides and metals using sequential removal on multiple polish platens to increase equipment throughput. U.S. Pat. No. 5,852,497 to the common assignee of this patent application discusses Shallow Trench Isolation (STI) for semiconductor manufacture wherein chemical mechanical polishing (CMP) is utilized to planarize the topography of the alignment marks. Because the polysilicon layer is opaque to the conventional white light source and the HeNe source, and because the alignment marks have been planarized, boundaries between different materials are used to form the alignment marks.
During the manufacture of silicon wafers for use in the fabrication of integrated circuits the wafers must be planarized. CMP is a process to planarize the surface of silicon wafers during production. With CMP, the planarization is accomplished by bringing the surface of the wafer in contact with a polishing pad and introducing a slurry to remove some of the surface. When the process is completed, the surface of the wafer is flat, and the slurry is removed by inducing a slurry rinse fluid, usually Deionized Water. The wafer is then removed from the system to be cleaned and sent on for additional processing. However, due to the flatness of the wafer, the flatness of the pad, and the liquid between the wafer and pad, removal of the wafer may not be successful.
In view of the foregoing, what is desired is an improved method and apparatus for manufacturing silicon wafers that provides for the simple and effective removal of wafers from the pad during the planarization process.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention discloses an apparatus for use in Chemical Mechanical Polishing for semiconductor manufacture, that can induce very small bubbles of gas into a stream of deionized water without allowing large bubbles to be entrained. The apparatus includes a cylinder possessing a central axis positioned vertically, a gas inlet, a fluid inlet positioned essentially above the gas inlet, a fluid and gas outlet positioned essentially above the deionized water inlet and a vent outlet positioned essentially above the fluid and gas outlet. The apparatus introduces an essentially gaseous composition into the cylinder through the gas inlet in
Caton Oscar L.
Wood Alexander P.
Eley Timothy V.
VLSI Technology Inc.
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