System for creating new group of chain descriptors by updating l

Details System for creating new group of chain descriptors by updating l System for creating new group of chain descriptors by updating l

1995-12-19

1998-01-27

Meky, Moustafa M.

G06F 1502

Patent

active

057130442

ABSTRACT:
Dynamic appending of chain descriptors is described with reference to a computer system having a host processor, a DMA unit, a host memory and an external memory wherein the DMA unit controls transference of data between the host memory and the external memory based upon data transference parameters specified in chain descriptors created by the host processor and stored as data structures within the host memory. In accordance with one method and apparatus described herein, dynamic appending of chain descriptors is achieved by employing a resume bit stored within a register of the DMA unit. The host processor, upon creating a new group of chain descriptors to be appended to a previous group, updates a link value within a last chain descriptor of the previous group to point to the first chain descriptor of the new group and also sets the resume bit within the DMA unit. The DMA unit reads chain descriptor parameters, including link values, they perform a data transfer operation specified by the chain descriptor parameters. Upon completion of the transfer operation, the DMA unit examines the resume bit and, if set, the DMA unit rereads the link value for the current chain descriptor. If the resume bit has not been reset, the DMA unit merely proceeds to process the next chain descriptor specified by the previously read link value or, if that link value is a null value, the DMA unit merely terminates operation. In an alternative embodiment described herein, the host processor updates link values but does not set a resume bit within the DMA unit. Rather, the DMA unit initially reads all parameters for a chain descriptor except for the link value. Then, after completion of the data transfer operation specified by the chain descriptor, the data unit reaccesses the chain descriptor to read the link value. Hence, if the link value is updated by the host processor while the DMA unit is processing a chain descriptor, the DMA unit will nevertheless access the updated link value upon completion of the data transference operation. Method and apparatus embodiments are described herein.

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patent: 5251312 (1993-10-01), Sodos
patent: 5367639 (1994-11-01), Sodos
patent: 5438665 (1995-08-01), Taniai et al.
patent: 5448702 (1995-09-01), Garcia, Jr. et al.
patent: 5513368 (1996-04-01), Garcia, Jr. et al.
patent: 5542053 (1996-07-01), Bland et al.

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