System for controlling the storage of information in a cache mem

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Details

36424341, 3642594, 3642645, 364DIG1, G06F 1300

Patent

active

050918451

ABSTRACT:
The invention provides a system for controlling the storage of information in a cache memory and features a processor to be connected to a bus, the bus including information signal transfer lines for transferring information signals and a cache control signal transfer line for transferring a cache control signal having a plurality of conditions, the processor including a cache memory and a bus interface circuit connected to the cache memory and for connection to the bus, the bus interface circuit including: i. an information signal transfer circuit for performing a read operation in which it receives information signals from the information signal transfer lines, the information signal transfer circuit transferring the received information signals to the cache memory; and ii. a cache control circuit connected to the cache memory and the information signal transfer circuit and for connection to the cache control signal transfer line for controlling whether the received information is to be stored in the cache memory in response to the condition of the cache control signal.

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