System for controlling mode of operation of a data cache based o

Details System for controlling mode of operation of a data cache based o System for controlling mode of operation of a data cache based o

1995-02-21

1997-07-29

Lee, Thomas C.

Boots, shoes, and leggings

395450, 395469, 36424341, 3642384, 3642423, 3642592, G06F 1300

Patent

active

056529155

ABSTRACT:
A computer system for controlling the mode of operation of a data cache. When a DMA state machine detects a DMA cycle to a memory block, the machine interrupts the processor so the processor sets a new value of the DMA state to control the mode of cache operation associated with the block.

REFERENCES:
patent: 4665506 (1987-05-01), Cline et al.
patent: 4899275 (1990-02-01), Sachs et al.
patent: 4977498 (1990-12-01), Rastegar et al.
patent: 5025366 (1991-06-01), Baror
patent: 5091846 (1992-02-01), Sachs et al.
patent: 5218686 (1993-06-01), Thayer
patent: 5230070 (1993-07-01), Liu
patent: 5247648 (1993-09-01), Watkins et al.
patent: 5255384 (1993-10-01), Sachs et al.
patent: 5325504 (1994-06-01), Tipley et al.
patent: 5353428 (1994-10-01), Shibata
patent: 5371872 (1994-12-01), Larsen et al.
patent: 5381538 (1995-01-01), Animi et al.
patent: 5392391 (1995-02-01), Caulk, Jr. et al.
patent: 5404489 (1995-04-01), Woods et al.
patent: 5469555 (1995-11-01), Ghosh et al.
Motorola, Section 7, "Instruction and Data Caches," MC68040 32-Bit Microprocessor User's Manual (1989).

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