System for controlling an internally-installed cache memory

Details System for controlling an internally-installed cache memory System for controlling an internally-installed cache memory

1995-03-20

1996-05-14

Swann, Tod R.

Boots, shoes, and leggings

39542102, 3954211, 395445, 36424341, 36424344, 3642478, 3642513, 3642551, 3642566, 364DIG1, G06F 1206, G06F 1300

Patent

active

055176330

ABSTRACT:
A cache uses A bits of an offset portion which are not subjected to the address translation of the logical address and B bits of the portion other than the offset portion, which are subjected to an address translation. It has an address monitor portion having a tag portion corresponding to the tag portion of the CPU using only A bits of the offset portion of the set address which are used as the set address in the cache and having a 2.sup.B .times.N-way set associative structure and a portion for making said tag portion of the cache correspond to said tag portion of the address monitor portion, thereby performing management of N address stored in the tag portion of the address monitor portion and transmitting the result of the management of the address to the cache and for invalidating the corresponding recording portion of the tag in the cache.

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Proceedings of IEEE International Conference on Computer Design: VLSI In Computers & Processors 1987, Washington, IEEE Comp. Soc. Press; US pp. 168-172; Alpert et al: Architecture of the NS32532 Microprocessor *p. 171, left column, line 31--right column line 11; FIGS 4, 5*.

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