System for controlling address keys under interrupt conditions

Details System for controlling address keys under interrupt conditions System for controlling address keys under interrupt conditions

1976-04-30

1977-07-19

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 920

Patent

active

040372073

ABSTRACT:
A control circuit arrangement for storing the addressability defined by the current active address key (AAK) being accessed in an address key register (AKR) in a processor. This AAK is stored in a last AAK register. When a hard or soft check interrupt occurs, the AAK stored in the last AAK register is designated as the processor's last key saved (i.e. LKSA) to define an interrupted addressability being used by the processor at the time of an interrupt. Upon occurrence of an interrupt, the LSKA represents the interrupted addressability, which is then made available to the processor by gating the LKSA into a source operand key section in the AKR from the processor's last AAK register, and setting the key for a supervisor program into another section of the AKR, so that the supervisor program can take corrective or termination actions. Until the LKSA gating into the AKR is completed, no AAK can be ingated into the last AAK register. After this in gating to the AKR is completed, the ingating disablement to the last AAK register is released.

REFERENCES:
patent: 3566358 (1971-02-01), Hasbrouck
patent: 3771146 (1973-09-01), Cotton et al.
patent: 3828327 (1974-08-01), Berglund et al.

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