System for controlling access to computer bus having address pha

Details System for controlling access to computer bus having address pha System for controlling access to computer bus having address pha

1985-11-15

1990-03-13

Lee, Thomas C.

Boots, shoes, and leggings

3642292, 3642404, 36424292, 3642612, 34082550, G06F 1342, G06F 1338, G06F 1318

Patent

active

049087495

ABSTRACT:
A computing system is disclosed which uses a system busy signal on its system bus to help control access to said bus. One or more requesters can generate a request signal when the system busy signal is not asserted. System busy is asserted along with the request signal(s) and remains asserted until all requesters which generated a request signal have gained access to the bus in order of priority. A freeze signal is generated on the system bus during the address phase of an instruction and a wait signal is generated during each data transfer in the data phase of an instruction. The freeze signal may be generated by a memory control unit, a memory module or a requester.

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