System for combining data from multiple CPU write requests via b

Details System for combining data from multiple CPU write requests via b System for combining data from multiple CPU write requests via b

1992-06-26

1995-10-17

Lee, Thomas C.

Boots, shoes, and leggings

395482, 395494, 395481, 395888, 3642523, 3642526, 3642527, 364DIG1, G06F 1314

Patent

active

054598427

ABSTRACT:
A write compression buffer is connected to a CPU bus and to a memory controller to provide write cycle compression in which plural partial write requests to the same memory address are compressed into a single memory write cycle. The buffer has a plurality of buffering level.

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L. Johnson et al, "Improved Video RAM Read Transfer Cycle", IBM TDB Jun. 1991, pp. 479-480.
R. J. Bowater et al, "Techniques for Dynamic RAM Bandwidth Utilization", IBM TDB Dec. 1984, pp. 4544-4545.

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