System for clock recovery

Details System for clock recovery System for clock recovery

1999-02-26

2002-04-23

Pham, Chi (Department: 2631)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S354000, C375S344000, C375S371000

Reexamination Certificate

active

06377642

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to a system for accurately decoding data, and more particularly to clock recovery system for maintaining the optimum time for sampling a signal.
BACKGROUND OF THE INVENTION
Communications technology has been advancing at a very fast pace in recent years. One such area of communications technology that has seen rapid development and implementation has been wireless communications, such as wireless local area networks (LANs) and metropolitan area networks. For wireless local area networks (LANs) and metropolitan area networks, two modulation techniques have come into widespread use, namely, direct sequence spread spectrum (DSSS) and frequency-hopping spread spectrum (FHSS). The physical layer specification (PHY) for DSSS and FHSS are defined by IEEE standard 802.11, which specifies the medium access control (MAC) and physical characteristics for wireless local area networks (LANs).
In accordance with IEEE standard 802.11 (which is fully incorporated herein by reference), the DSSS system provides a wireless LAN with both a 1 Mbps and a 2 Mbps data rate communication capability. The DSSS system uses modulations of differential binary phase shift keying (DBPSK) and differential quadrature phase shift keying (DQPSK) to provide the 1 and 2 Mbps data rates, respectively. In accordance with IEEE standard 802.11, the FHSS system also provides a wireless LAN with both 1 Mbps and a 2 Mbps data rate communication capability. However, the FHSS system uses two-level Gaussian frequency shift key (GFSK) modulation for 1 Mbps data rates, and four-level Gaussian frequency shift key (GFSK) modulation for 2 Mbps data rates. Thus, in two-level GFSK (2GFSK) the incoming bit stream is converted to 1 bit words or symbols (0, 1), and in four-level GFSK (4GFSK) the incoming bit stream is converted to 2 bit words or symbols (00, 01, 11, 10). It should be appreciated that for 4GFSK the 2 bit symbols are Gray code (i.e., adjacent symbol levels only differ in only one bit), in order to minimize errors.
A typical wireless communications system generally operates as follows. A transmitting device encodes a symbol as an analog signal. This analog signal is then upconverted in frequency to be transmitted to a receiving device via a wireless medium. The receiving device downconverts the analog signal to a lower frequency, passes it through a limiter and discriminator circuit to remove the FM modulation. The resulting waveform is converted into digital values using an analog-to-digital converter (ADC). The digital values form an input waveform that is decoded to recover the symbols originating from the transmitting device. In order to properly decode the input waveform, the input waveform must be sampled during an appropriate interval. In this regard, the input waveform is preferably sampled at a time when the input waveform is at maximum separation from an input waveform for the nearest (or adjacent) symbol. Distinguishing between input waveforms for adjacent symbols is made difficult due to fading, signal dropout, noise and interference, which are commonplace in signals transmitted via a wireless medium. Problems are also encountered as a result of oscillator drift.
In the prior art a phase-locked loop (PLL) is frequently utilized to decode waveforms such as those described above. A PLL includes a phase detector, amplifier, and voltage controlled oscillator (VCO). The phase detector compares two input frequencies (f
IN
of the input signal and f
VCO
of the VCO), generating a phase-error signal that is a measure of their phase difference. The phase-error signal is filtered and input to the amplifier to generate a control voltage. For example, the phase-error signal may be a periodic output at the difference frequency. If f
IN
does not equal f
VCO
, the phase-error signal, after being filtered and amplified, causes the VCO frequency (f
VCO
) to deviate in the direction of f
IN
. If conditions are right, the VCO will quickly “lock” to f
IN
, maintaining a fixed phase relationship with the input signal. As a result, the filtered output of the phase detector is a dc signal, and the control voltage input to the VCO is a measure of the input frequency f
IN
. However, the PLL has several drawbacks, including frequency drift with temperature variations and frequency variations during long runs of the same bit pattern.
The present invention addresses these and other decoding problems encountered in the prior art, to provide a system for clock recovery.
SUMMARY OF THE INVENTION
According to the present invention there is provided a decoding system for decoding a received input waveform including a plurality of encoded symbols, the decoding system comprising: sampling means for sampling an input waveform for a plurality of sample cycles, wherein for each sample cycle a zero-crossing input value is obtained at a first sampling time and a sampled input value is obtained at a second sampling time; decoding means for decoding each sampled input value into a decoded symbol; symbol evaluation means for comparing the decoded symbol from a current sample cycle to the decoded symbol from a previous sample cycle; means for determining an accumulated offset value, in accordance with the character of the transition between the decoded symbol from a current sample cycle to the decoded symbol from a previous sample cycle; and timing modification means for modifying one of said first and second sampling time of at least one sample cycle in response to said accumulated offset value exceeding at least one predetermined threshold value.
According to another aspect of the present invention there is provided a method for decoding a received input waveform including a plurality of encoded symbols, the method comprising: sampling an input waveform for a plurality of sample cycles, wherein for each sample cycle a zero-crossing input value is obtained at a first sampling time and a sampled input value is obtained at a second sampling time; decoding each sampled input value into a decoded symbol; comparing the decoded symbol from a current sample cycle to the decoded symbol from a previous sample cycle; determining an accumulated offset value, in accordance with the character of the transition between the decoded symbol from a current sample cycle to the decoded symbol from a previous sample cycle; and modifying one of said first and second sampling times of at least one sample cycle in response to said accumulated offset value exceeding at least one predetermined threshold value.
An advantage of the present invention is the provision of a clock recovery system which is stable with temperature variations and maintains a stable frequency independent of data pattern.
Another advantage of the present invention is the provision of a clock recovery system which minimizes power consumption;
Still another advantage of the present invention is the provision of a clock recovery system which is inexpensive to manufacture;
Still other advantages of the invention will become apparent to those skilled in the art upon a reading and understanding of the following detailed description, accompanying drawings and appended claims.


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