System for automatic testing of circuits and systems

Details System for automatic testing of circuits and systems System for automatic testing of circuits and systems

1983-11-25

1987-04-07

Atkinson, Charles E.

Excavating

324 73AT, 364580, 371 25, G01R 3128

Patent

active

046566325

ABSTRACT:
A Universal Pin Electronics ("UPE") System is disclosed which incorporates a plurality of testing channels, each of which is coupled to a single input pin of a unit under test and is capable of selectively generating a plurality of different types of stimuli and applying the same to the single pin of the unit under test. The test channels are also coupled to a single output pin of the unit under test and are capable of receiving an induced output from the unit being tested. Test channels may be coupled to a common single pin of the unit under test which pin is capable of functioning as a bidirectional pin. In a preferred embodiment, each test channel has the capability of selectively generating functional digital, parametric digital and analog stimuli, applying the same to a pin of the unit under test, and receiving the output of the same or a different pin and comparing it with the expected output or storing it. The test channel includes a local memory which receives and stores digital information corresponding to functional digital, parametric digital, and analog stimuli to be generated by the test channel. The digital information is loaded into the local memory under control of a local microcontroller. The local memory is large enough to store a substantial quantity of digital information without replenishment so that the test channel is capable of conducting relatively extensive testing with respect to the pin of the unit under test to which it is coupled. The local memory can store compacted data and the UPE can include a decompaction circuit. Each UPE test channel can accomplish at its associated pin, without switching: functional digital stimulus generation; functional digital measurement; functional digital stimulus generation and measurement; parametric digital stimulus generation; parametric digital measurement; analog stimulus generation; and analog measurement.

REFERENCES:
patent: 3657527 (1972-04-01), Kassabgi et al.
patent: 3714571 (1973-01-01), Walker
patent: 3832535 (1974-08-01), DeVito
patent: 3854125 (1974-10-01), Ehling et al.
patent: 3922537 (1975-11-01), Jackson
patent: 3976940 (1976-08-01), Chau et al.
patent: 4000460 (1976-12-01), Kadakia et al.
patent: 4044244 (1977-08-01), Foreman et al.
patent: 4055801 (1977-10-01), Pike et al.
patent: 4102491 (1978-07-01), De Vito et al.
patent: 4155116 (1979-05-01), Tawfik et al.
patent: 4168527 (1979-09-01), Winkler
patent: 4313200 (1982-01-01), Nishiura
Jackson, Philip C., "Evolutionary Trends In Pin Electronics", IEEE Publication No. CH 1488-6/79/0000-0018 (1979), pp. 18-22.
Research and Development Technical Report GECOM-81-0146-F "Universal Pin Electronics", Sep., 1982.

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