System for assigning positions of block terminals in a VLSI

Details System for assigning positions of block terminals in a VLSI System for assigning positions of block terminals in a VLSI

1993-03-25

1995-04-04

Trans, Vincent N.

Boots, shoes, and leggings

364490, 364489, 364488, G06F 1560

Patent

active

054043131

ABSTRACT:
A system in which blocks are classified into one or more fixed shape blocks in which terminal positions are previously determined and one or more variable shape blocks in which terminal positions are changeable. The system includes an initial terminal assign section for provisionally assigning terminal positions relating to the variable shape blocks for the purpose of minimizing the total length of the wirings; and a terminal distribution and assign section for evaluating the provisionally assigned terminal positions and for distributing the provisionally assigned terminal positions on the basis of the evaluation.

REFERENCES:
patent: 3629843 (1971-12-01), Scheinman
patent: 4577276 (1986-03-01), Dunlop et al.
patent: 4593363 (1986-06-01), Burstein et al.
patent: 4839821 (1989-06-01), Murakata
patent: 4908772 (1990-03-01), Chi
Eugene L. Lawler, "Combinatorial Optimization: Networks and Matroids", 1976, pp. 109-132.
Ulrich Ph. Lauter, "Top Hierarchical Global Routing For Channelless Gate Arrays Based on Linear Assignment", (1987).
"A Block Interconnection Algorithm for Hierarchical Layout System" by Fukui et al., IEEE Trans. on C.A.D., vol. CAD-6, No. 3, May 1987, pp. 383-390.
"Automatic Placement and Routing of Gate Arrays" by G. Robson, VLSI Design, vol. V, No. 4, Apr. 1984, pp. 35-43.
"A Routing Program Applicable to Various Chip Structures of Gate Arrays" by Terai et al., Joho Shori Gakkai, Ronbunshi, vol. 25, No. 3, May 1984, pp. 357-364.

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