System for assigning interrupts to least busy processor that alr

Details System for assigning interrupts to least busy processor that alr System for assigning interrupts to least busy processor that alr

1988-05-16

1990-09-25

Williams, Jr., Archie E.

Boots, shoes, and leggings

3642281, 3642302, 3642379, 3642447, 3642463, 3642632, G06F 946, G06F 1314, G06F 1324, G06F 1516

Patent

active

049597817

ABSTRACT:
An apparatus and method for processing of interrupts in a computer system includes interrupts which are presented substantially simultaneously to each of a plurality of processors in the computer system. Each of the plurality of processors may respond to the interrupts and the first processor assigned to handle the interrupt prevents the other processors from handling the interrupts. The present invention further discloses means for disabling processors from responding to interrupts.

REFERENCES:
patent: 4153934 (1979-05-01), Sato
patent: 4268904 (1981-05-01), Suzuki et al.
patent: 4271468 (1981-06-01), Christensen et al.
patent: 4426681 (1984-01-01), Bacot et al.
patent: 4630193 (1986-12-01), Kris
patent: 4638432 (1987-01-01), Niblock et al.
patent: 4779195 (1988-10-01), James

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