System for arbitrating access to memory with dynamic priority as

Details System for arbitrating access to memory with dynamic priority as System for arbitrating access to memory with dynamic priority as

1994-10-14

1996-06-04

Swann, Tod R.

395293, 395296, 395729, 395732, G06F 1318

Patent

active

055242359

ABSTRACT:
An arbiter circuit for controlling access to the main memory for requests asserted by the microprocessor, the refresh controller and PCI bus masters. Generally, the priority of the memory requests are as follows, with some exceptions: (1) second refresh request; (2) processor-to-memory write request; (3) memory-to-processor read request; (4) PCI-to-memory write request; (5) memory-to-PCI read request; and (6) first refresh request. The second refresh request indicates that two refreshes are outstanding. When that occurs, both outstanding refresh requests are assigned the highest priority. The processor-to-memory write request is always higher in priority than other memory requests except the second refresh. However, under certain conditions, the processor-to-memory write requests is held off to allow other cycles to proceed. The memory-to-processor read request is generally higher in priority than the PCI write and read requests, unless certain conditions occur to override that priority. PCI-to-memory write requests are always higher in priority than memory-to-PCI read requests.

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